
210 An Introduction to Compiler Construction in a Java World
branches, delayed loads, caching, and memory latency. Fortunately, the MIPS assembler
models a virtual machine that both hides these timing issues and uses pseudo-instructions
to provide a slightly richer instruction set. By default, SPIM simulates this virtual machine,
although it can be configured to model the more complicated raw MIPS computer. We will
make use of the simpler, default assembly language.
6.2.2 Memory Organization
Memory is, by convention, divided into four segments, as illustrated in Figure 6.3 and
derived from [Larus, 2009].
FIGURE 6.3 SPIM memory organization.
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