Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL

5.4 NMOS AND PMOS LOGIC GATES

5.4.1 NMOS Inverter

Consider the circuit shown in Figure 5.4. The operation of the circuit can be explained as follows. When V_G = 0V (logic 0), the NMOS transistor T₁ is off and no current flows through resistor R. The output voltage V_out is equal to V_DD (logic 1). However, if V_G = V_DD (logic 1), the NMOS switch is closed and the NMOS transistor T₁ starts conducting, thereby pulling down the output node to ground. Thus, the output voltage is logic 0. The circuit in Figure 5.4 acts as an inverter gate. The purpose of resistor R is to limit the current when the NMOS transistor is turned on. In other words, this resistor acts as a current source load. It will be replaced with a PMOS transistor in later circuit design. The truth table is also shown in Figure 5.4.

Figure 5.4 NMOS Inverter Gate and Its Truth Table

5.4.2 NMOS NAND Gate

Now observe the circuit diagram shown in Figure 5.5. Consider the case when both inputs are high (i.e., logic 1) and NMOS transistors T₁ and T₂ are both turned, pulling the output node down to ground, resulting in logic 0 as output. On the other hand, if any one of the inputs or both inputs is low (i.e., logic 0), one or both transistors will be turned off and act as an open switch, and thus the output will remain high (i.e., logic 1). The resulting truth table for this circuit is also shown in Figure 5.5, which is the same ...