Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL

9.9.1 D Flip-Flop Implementation

To implement the 3-bit up counter, the final step of design is to choose the appropriate flip-flops. Of course, the simplest choice is to use D flip-flops. However, D flip-flops may not yield simple combinational logic, and other flip-flops must be considered as well. We will design the counter using D, JK, and T flip-flops.

Figure 9.46 shows a circuit implementation of the 3-bit counter using D flip-flops. Each next state is connected to the D input of the flip-flop, which provides the present state of the same variable. Notice that the combination logic requires a large number of logic gates. The complexity of the combinational logic will increase as the size of the counter increases. Figure 9.46 shows two-level logic design, but as the size of the counter increases, the fan-in and fan-out become serious problems that need to be addressed. When designing with discrete components, other flip-flops must be considered to minimize the combinational logic. Next, we attempt to reduce the combinational logic by using JK and T flip-flops.

9.9.2 JK Flip-Flop Implementation

JK flip-flops have been used widely in the past to implement digital counters. They can be configured (wired) to operate as D, SR, or T flip-flops. Recall that the next states are the inputs of the flip-flops, and the present states are the outputs of the flip-flops. Therefore, to use JK flip-flops to implement sequential circuits, inputs J and K must be determined from the output states ...