List of Figures
1.1 The reconfigurable NoC architecture (a) and three possible switch configurations (b).
1.2 Flits traverse the connection between nodes X and Y (the black solid line) in five cycles in a pipelined fashion. Flits are buffered at the black switches.
1.3 The implementation of a mesh on the reconfigurable topology among all network nodes (a) and a selected set of cores, where the black nodes are active and the gray cores are inactive (dark) (b).
1.4 The area overhead of the reconfigurable NoC for different buffer depths (flits), network sizes (number of nodes), and link widths (bits).
1.5 Reconfigurable NoC with the corridor width of 2 (a) and a cluster-based reconfigurable NoC with cluster size of 4 (b).
1.6 The generalized cluster-based reconfigurable structure.
1.7 The communication task graph and corresponding topology for MP3 (encoder+decoder) (a), H263 decoder (b), H63 encoder (c).
1.8 Power consumption (Watts) and packet latency (cycles for 8-flit packets) in a conventional and a reconfigurable NoC. The conventional NoC uses NMAP.
1.9 The average message latency (cycles for 8-flit packets) (a) and power (Watts) (b) of the three NoC configurations with the same area under the MMS traffic and its variants.
1.10 The average message latency (cycles for 8-flit packets) (a) and power (Watts) (b) of the three NoC configurations.
1.11 Comparing the average message latency (cycles for 8-flit packets) (a) and power (Watts) (b) with the CMesh topology.
2.1 CUDA grid ...
