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Low-Voltage SOI CMOS VLSI Devices and Circuits by James B. Kuo, Shih-Chia Lin

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Fundamentals of SOI CMOS Circuits

Until now, behaviors of the SOI CMOS devices were described in Chapters 2 and 3. In the next three chapters, digital and analog circuits implemented by SOI CMOS devices are depicted. In this chapter, basic knowledge of SOI CMOS circuits is described. Starting from the basic circuit issues, the floating body effects on the performance of the SOI CMOS circuits are explained, followed by the low-voltage SOI CMOS circuits, SOI dynamic-threshold MOS (DTMOS) circuits, and SOI multithreshold MOS (MTMOS) circuits. Then, noise and self-heating problems of SOI CMOS circuits are analyzed. Finally, the SOI ESD circuits and the SOI system-on-a chip (SOC) technology are presented.

4.1 BASIC CIRCUIT ISSUES

Compared to conventional bulk circuits, SOI CMOS devices offer more advantages for designing low-voltage VLSI circuits. Owing to the buried oxide structure to isolate the thin film from the substrate, the CMOS latchup phenomena frequently encountered in bulk CMOS structures can be avoided. Owing to the buried oxide, the parasitic capacitances in the source/drain regions are reduced. Due to the thin-film structure, SOI CMOS devices have a better performance in subthreshold slope and transconductance. The leakage current is smaller for the SOI CMOS devices owing to the oxide isolation structure. In addition, the buried oxide structure can also be used to improve ...

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