SOI CMOS Digital Circuits

SOI CMOS technology has been used to integrated VLSI digital circuits owing to its advantages. In this chapter, starting from fundamental SOI CMOS static and dynamic logic circuits, DRAM and SRAM circuits using SOI CMOS technology are described. Then, SOI cache memory and content addressable memory (CAM) are depicted, followed by SOI gate arrays. SOI CPU and embedded memory are introduced, and finally SOI multipliers/digital signal processing (DSP) circuits, and SOI frequency dividers.


As shown in Fig. 5.1, a static CMOS logic circuit is composed of pullup and pull-down switches Su/Sd, cross-coupled element (CC), an extra resistive load and an active path to the power supply voltages VDD/GND. Using the concept of the generic static CMOS logic gate, Fig. 5.2 shows the various differential static CMOS gates implementing XOR logic in terms of (a) standard CMOS, (b) push~pull cascode logic (PPCL), and (c) complementary pass transistor logic (CPL). Among three differential static CMOS gates, CPL has the smallest transistor count, since the input signal is passed via the gate or the source/drain of a single NMOS device. It has small parasitic capacitances. Due to the reduced threshold voltage using the body control schemes, PD SOI CMOS devices are suitable for use to integrate CPL circuits since the output swing of the CPL is close ...

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