O'Reilly logo

Low-Voltage SOI CMOS VLSI Devices and Circuits by James B. Kuo, Shih-Chia Lin

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

7

images

PD SOI-Technology SPICE Models

In this chapter, PD SOI-Technology SPICE models using a concise BiCMOS approach are described. In following sections, the PD SOI SPICE models are described first, followed by the kink effects, the hysteresis behavior and the transient behavior using the PD SOI-Technology SPICE models. In the final portion of this chapter, in order to show the effectiveness of the PD SOI-Technology SPICE models, the behaviors of a static logic circuit, a dynamic logic circuit, and an SRAM critical path are analyzed using the PD SOI-Technology SPICE models.

7.1 PD SOI SPICE MODEL

Fig. 7.1 shows the cross-section of the partially depleted (PD) SOI NMOS device under study and the PD SOI-Technology SPICE models1 using a concise BiCMOS approach. As shown in this figure, the PD SOI-Technology SPICE models are composed of the surface MOS device and the parasitic bipolar device connected in parallel, considering the neutral region in the thin film. The emitter of the parasitic BJT and the source of the surface MOS device are connected together (S). In addition, the collector of the parasitic BJT and the drain of the surface MOS device share the same terminal (D). The base of the parasitic BJT, which is connected to the substrate of the surface MOS device, becomes a floating body node (B). A capacitor (Cburied) has been adopted to account for the effect of the buried oxide. ...

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required