book

Nonvolatile Memory Design

by Hai Li, Yiran Chen

December 2017

Intermediate to advanced

208 pages

5h 36m

English

CRC Press

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1.1 Classification and Characterization of Semiconductor Memories1.1.1 Read-Only Memory1.1.2 Erasable Programmable ROM and Flash Memory1.1.3 Electrically Erasable Programmable ROM1.1.4 Static RAM1.1.5 Dynamic RAM1.1.6 Nonvolatile Memories1.1.6.1 Phase Change Memory1.1.6.2 Magnetic Random Access Memories1.1.6.3 Resistive RAM1.1.6.4 Memristor1.2 Devices1.2.1 MOSFET1.2.1.1 Cutoff Regions1.2.1.2 Triode Region1.2.1.3 Saturation Region1.2.2 Diode1.2.3 Passive Component1.2.3.1 Capacitor1.2.3.2 Resistor1.3 Designing Memory and Array Structures1.3.1 Memory Architecture and Building Blocks1.3.1.1 Memory Cell Array1.3.1.2 I/O Interface1.3.2 Memory Peripheral Circuitry1.3.2.1 Decoder1.3.2.2 Sense Amplifier1.3.2.3 Write Driver1.3.3 Memory Reliability and Yield1.3.3.1 Reliability1.3.3.2 Yield1.3.4 TestingReferences
2.1 Introduction to PCM2.1.1 Phase Change Properties2.1.2 History of PCM2.1.3 Phase Change Operation2.2 Material Research2.2.1 Ge2Sb2Te5 Alloys2.2.2 Doped GST2.2.3 GeSb Material2.3 Device Research2.3.1 Bridge Cell2.3.2 Pillar Cell2.3.3 Pore Cell2.4 Electrothermal Modeling2.4.1 PCM Design Technique2.4.1.1 Access Device of PCM Bit Cell2.4.1.2 Multilevel Cell2.4.2 Program Algorithm2.4.3 Read and Other Peripheral Circuitry2.4.4 Physical Limit of PCM2.4.4.1 Bit Retention2.4.4.2 Bit Endurance2.4.4.3 Continue Moore’s LawReferences
3.1 Introduction of Spin -Transfer Torque Technology3.1.1 Spin-Transfer Torque Theory3.1.2 Dynamic Behavior of an MTJ3.1.3 Some Important Parameters of MTJ3.1.3.1 RH, RL, RAP, and Tunneling Magnetoresistance3.1.3.2 Aspect Ratio3.1.3.3 Resistance-Area Product3.1.3.4 Switching Current IC3.1.3.5 MTJ Switching Probability Psw3.2 Spin-Transfer Torque Random Access Memory3.2.1 Basic Structure3.2.2 Write and Read Mechanism3.3 STT-RAM Architecture3.4 STT-RAM Modeling3.4.1 Dynamic MTJ Modeling3.4.2 Cell Modeling3.5 Design Challenges3.5.1 Sources of Process Variations3.5.1.1 CMOS Process Variations3.5.1.2 MTJ Resistance Variations3.5.1.3 Switching Current Variations3.5.2 Static Failures in STT-RAM3.6 Design Techniques of STT-RAM3.6.1 STT-RAM Cell3.6.1.1 Other STT-RAM Cell Designs3.6.1.2 STT-RAM Cell Scalability3.6.1.3 Variation Control of STT-RAM Bit Cell3.6.2 STT-RAM Circuit Design—Self-Reference Scheme3.6.2.1 Conventional Sensing Scheme3.6.2.2 Conventional Self-Reference Sensing Scheme3.6.2.3 Nondestructive Self-Reference Sensing Scheme3.6.2.4 Voltage-Driven Nondestructive Self-Reference Sensing Scheme3.6.2.5 Comparison of Different Sensing Schemes3.6.3 STT-RAM Architecture Design Technique3.6.3.1 Read-Before-Write Scheme3.6.3.2 Early Write Termination3.6.3.3 Data Inverting3.6.3.4 Wear Leveling3.6.3.5 Dual Write-Speed Method3.7 Multilevel Cell3.7.1 Write Scheme for Multilevel Cells3.7.1.1 Simple Write Scheme of MLC STT-RAM Cells3.7.1.2 Complex Write Scheme of MLC STT-RAM Cells3.7.1.3 Hybrid Write Scheme of MLC STT-RAM Cells3.7.2 Sensing Scheme for MLCReferences
4.1 Variety of R-RAM4.1.1 Electrochemical Metallization Devices4.1.2 Valence Change System4.2 R-RAM Operations4.3 Single Cell R-RAM Design4.3.1 Crossbar Structure Design without Switching Device4.3.2 R-RAM Cell Design with Active Switching Device4.3.3 R-RAM Cell Design with Passive Switching Device4.4 R-RAM Scalability4.4.1 Basic Memory Structure and Its Fabrication4.4.2 Statistics of RSD Resistance4.4.3 Electrical Properties4.5 R-RAM Array Structure4.5.1 Conventional Crossbar Array4.5.2 Complementary Crossbar Structure4.6 3D Stacking R-RAM4.6.1 3D Unipolar R-RAM Design4.6.2 3D Bipolar R-RAM Design4.6.3 3D High-Density Interleaved Memory Design4.6.3.1 Read Operation4.6.3.2 Write Operation4.6.3.3 Impact of Data Patterns4.6.3.4 Impact of Cell Location4.7 Summary and FutureReferences

5.1 Memristor Theory5.2 Metal-Oxide Memristor5.2.1 Titanium Dioxide as Memristor5.2.2 Other Oxide-Based Memristor Options5.3 Spintronic Memristor5.3.1 Spintronic Device as Memristor5.3.2 Compact Model of Spintronic Memristor5.3.2.1 Model of Spintronic Memristor5.3.2.2 Electrical Property of Spintronic Memristor5.3.2.3 Model Summary5.3.3 I-V Curve and Frequency Response5.3.3.1 M-q Curve5.3.3.2 Sinusoidal Wave Excitation5.3.3.3 Biased Sinusoidal Wave Excitation5.4 Applications and Future Trends5.4.1 Memristor Memory5.4.2 Memristor Thermal SensorReferences
6.1 Developments in Future Nonvolatile Memory Technologies6.1.1 Review of Current Efforts in the World6.2 Future Research Trends6.2.1 Who Will Be the Winner?6.2.2 Semiconductor Memory Roadmap6.2.3 ForecastReferences

Content preview from Nonvolatile Memory Design

Among all memory technologies introduced in this book, phase change memory (PCM) is probably the closest to the commercialization stage. Similarly, PCM has two or more distinct resistance states that represent the different logic values. Data storage, however, is based on switching between the amorphous phase with high electrical resistivity and the crystalline phase(s) with low electrical resistivity.

2.1 Introduction to PCM

2.1.1 Phase Change Properties

A phase-change material usually has two or more phases with quite different electrical properties, as shown in Figure 2.1. The materials can switch among these phases repeatedly and stably under some conditions; that is, under heating for certain lengths of time. As ...