6.2. Single-Phase Full-Bridge Inverter

The half-bridge inverter of Fig. 6.2(a) exhibits the following three major disadvantages:
i) Two electrolytic capacitors connected in series are needed at the dc input side.
ii) It is unable to generate zero output voltage intervals for nonresistive loads.
iii) The amplitude of the output voltage pulses is half of the dc input voltage.
Fig. 6.5(a) shows the power circuit of the single-phase full-bridge inverter (composed of two half-bridge inverters), which does not present any of the drawbacks mentioned above. Fig. 6.5(b) shows the gating pulses of the power semiconductor switches and the generated square-wave output voltage. Furthermore, Fig. 6.6 shows the gating signals and the generated quasi square-wave ...

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