SWITCH PERFORMANCE ANALYSIS AND DESIGN IMPROVEMENTS
This chapter first focuses on the performance analysis of some simple switch designs. From the analysis, we shall see that head-of-line (HOL) blocking as well as output contention among packets may severely limit the switch throughput. This chapter will then present several fundamental switch design principles to alleviate these problems and achieve performance improvement. Each switch design principle will be illustrated using specific implementations. Note, however, that many implementations are possible based on each switch design concept, and one should not confuse implementations with concepts.
4.1 PERFORMANCE OF SIMPLE SWITCH DESIGNS
This section analyzes the delay and throughput performance of some simple switch designs with an internally nonblocking structure. Since the packets are fixed-length, the arrivals can be aligned (as discussed at the beginning of the preceding chapter) with a maximum alignment delay of one-packet duration. With the alignment, we may assume in our analysis that time is slotted and that the packets arrive to the inputs at the beginning of each time slot.
For simplicity, we shall also assume a uniform-traffic distribution. Packet arrivals at the inputs are described by a simple Bernoulli process: in any time slot, the probability that a packet will arrive on a particular input is ρo. The parameter ρo is also referred to as the offered load. Each packet is destined for any given output with equal ...
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