book

Pulse and Digital Circuits

Name: Pulse and Digital Circuits
ISBN: 9788131721353

by Venkata Rao K., Rama Sudha K., Manmadha Rao G.

June 2010

Intermediate to advanced

721 pages

21h 32m

English

Pearson India

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Cover
Title Page
Contents
Dedication
Preface
1. An Introduction to Pulse Waveforms
1.1 Introduction
1.2 Current and Voltage Sources
1.3 Network Laws
1.3.1 Kirchoff’s Laws1.3.2 The Superposition Theorem1.3.3 Thévenin’s Theorem1.3.4 Norton’s Theorem
1.4 Devices, Characteristics and Applications
1.4.1 Diodes1.4.2 Bipolar Junction Transistors1.4.3 Amplifiers1.4.4 The Three Basic Amplifiers1.4.5 Multi-stage Amplifiers1.4.6 Feedback in Amplifiers1.4.7 Noise

1.5 Operational Amplifiers
1.6 Oscillators
1.7 CC Amplifier as a Power Amplifier
1.8 Miller’s Theorem
1.8.1 The Dual of Miller’s Theorem
1.9 Ground in a Circuit
1.10 Stray Capacitances in Devices
1.11 Field-effect Transistors
1.12 Characteristics of Pulse Waveforms
1.12.1 Types of Waveforms Used in Pulse Circuits1.12.2 Energy Storage Elements
1.13 Laplace Transforms
1.13.1 Basic Properties of Laplace Transformation
2. Linear Waveshaping: High-pass Circuits
2.1 Introduction
2.2 High-pass Circuits
2.2.1 Response of the High-pass RC Circuit to Sinusoidal Input2.2.2 Response of the High-pass RC Circuit to Step Input2.2.3 Response of the High-pass RC Circuit to Pulse Input2.2.4 Response of the High-pass RC Circuit to Square-wave Input2.2.5 Response of the High-pass RC Circuit to Exponential Input2.2.6 Response of the High-pass RC Circuit to Ramp Input
2.3 Differentiators
2.3.1 A High-pass RC Circuit as a Differentiator2.3.2 An Op-amp as a Differentiator2.3.3 Double Differentiators
2.4 The Response of a High-pass RL Circuit to Step Input
SummaryMultiple Choice QuestionsShort Answer QuestionsLong Answer QuestionsUnsolved Problems
3. Linear Waveshaping: Low-pass Circuits, Attenuators and RLC Circuits
3.1 Introduction
3.2 Low-pass Circuits
3.2.1 The Response of a Low-pass RC Circuit to Sinusoidal Input3.2.2 The Response of a Low-pass RC Circuit to Step Input3.2.3 The Response of a Low-pass RC Circuit to Pulse Input3.2.4 The Response of a Low-pass RC Circuit to a Square-wave Input3.2.5 The Response of a Low-pass RC Circuit to Exponential Input3.2.6 The Response of a Low-pass RC Circuit to Ramp Input3.2.7 A Low-pass RC Circuit as an Integrator3.2.8 An Op-amp as an Integrator3.2.9 Low-pass RL Circuits
3.3 Attenuators
3.3.1 Uncompensated Attenuators3.3.2 Compensated Attenuators
3.4 RLC Circuits
3.4.1 The Response of the RLC Parallel Circuit to a Step Input3.4.2 The Response of the RLC Series Circuit to a Step Input3.4.3 RLC Ringing CircuitsSummaryMultiple Choice QuestionsShort Answer QuestionsLong Answer QuestionsUnsolved Problems
4. Non-linear Waveshaping: Clipping Circuits and Comparators
4.1 Introduction
4.2 Diodes as Switches
4.2.1 The Semiconductor Diode as a Switch4.2.2 The Zener Diode as a Switch
4.3 Clipping Circuits
4.3.1 Series Clippers4.3.2 Shunt Clippers4.3.3 Two-level Clippers4.3.4 Noise Clippers
4.4 Comparators
4.4.1 Diode Comparators4.4.2 The Double Differentiator as a Comparator
4.5 Applications of Comparators
SummaryMultiple Choice QuestionsShort Answer QuestionsLong Answer QuestionsUnsolved Problems
5. Non-linear Waveshaping: Clamping Circuits
5.1 Introduction
5.2 The Clamping Circuit
5.2.1 The Clamping Circuit for Varying Input Amplitude5.2.2 The Practical Clamping Circuit5.2.3 Clamping the Output to a Reference Voltage (VR)5.2.4 The Design of a Clamping Circuit
5.3 The Effect of Diode Characteristics on the Clamping Voltage
5.4 Synchronized Clamping
5.5 The Clamping Circuit Theorem
SummaryMultiple Choice QuestionsShort Answer QuestionsLong Answer QuestionsUnsolved Problems
6. Switching Characteristics of Devices
6.1 Introduction
6.2 The Diode as a Switch
6.2.1 Diode Characteristics6.2.2 Transition Capacitance6.2.3 Diffusion Capacitance6.2.4 Junction Diode Switching Times6.2.5 Piecewise Linear Diode Model6.2.6 Breakdown Diodes
6.3 The Transistor as a Switch
6.3.1 The Transistor as an Open Switch6.3.2 The Transistor as a Closed Switch6.3.3 Over-driven Transistor Switches6.3.4 The Design of a Transistor Inverter
6.4 Switching Times of a Transistor
6.4.1 The Turn-on Time of a Transistor6.4.2 The Turn-off Time of a Transistor
6.5 Breakdown Voltages
6.5.1 The CE Configuration6.5.2 The Breakdown Voltage with Base Not Open Circuited
6.6 The Saturation Parameters of a Transistor and their Variation with Temperature
6.7 Latching in a Transistor Switch
6.8 Transistor Switches with Complex Loads
6.8.1 Switches with Inductive Loads6.8.2 Switches with Capacitive LoadsSummaryMultiple Choice QuestionsShort Answer QuestionsLong Answer QuestionsUnsolved Problems
7. Astable Multivibrators
7.1 Introduction
7.2 Collector-coupled Astable Multivibrators
7.2.1 Calculation of the Frequency of an Astable Multivibrator7.2.2 The Design of an Astable Multivibrator7.2.3 An Astable Multivibrator with Vertical Edges for Collector Waveforms
7.3 An Astable Multivibrator as a Voltage-controlled Oscillator
7.4 An Astable Multivibrator as a Frequency Modulator
7.5 Emitter-coupled Astable Multivibrators
7.5.1 Advantages of Emitter-coupled Astable Multivibrators7.5.2 Disadvantages of Emitter-coupled Astable MultivibratorsSummaryMultiple Choice QuestionsShort Answer QuestionsLong Answer QuestionsUnsolved Problems
8. Monostable Multivibrators
8.1 Introduction
8.2 Collector-coupled Monostable Multivibrators
8.2.1 Triggering a Monostable Multivibrator8.2.2 Calculation of the Time Period (T)8.2.3 The Effect of Temperature on Gate Width
8.3 Calculation of the Voltages to Plot the Waveforms
8.3.1 In the Stable State (t < 0)8.3.2 In the Quasi-stable State (t = 0+)8.3.3 At the End of the Quasi-stable State (at t = T +)8.3.4 The Design of a Collector-coupled Monostable Multivibrator
8.4 Commutating Condensers
8.4.1 Calculation of the Value of the Commutating Condenser8.4.2 A Monostable Multivibrator as a Voltage-to-time Converter
8.5 Emitter-coupled Monostable Multivibrators
8.5.1 To Calculate the Gate Width (T)8.5.2 To Calculate the Voltages8.5.3 The Design of an Emitter-coupled Monostable Multivibrator8.5.4 Free-running Operation of an Emitter-coupled Monostable MultivibratorSummaryMultiple Choice QuestionsShort Answer QuestionsLong Answer QuestionsUnsolved Problems
9. Bistable Multivibrators
9.1 Introduction
9.2 Bistable Multivibrator Circuits
9.2.1 Fixed-bias Bistable Multivibrators9.2.2 The Resolution Time and the Maximum Switching Speed of a Bistable Multivibrator9.2.3 Methods of Triggering a Bistable Multivibrator9.2.4 Non-saturating Bistable Multivibrators
9.3 Self-bias Bistable Multivibrators
9.3.1 The Heaviest Load Driven by a Self-bias Bistable Multivibrator9.3.2 The Design of a Self-bias Bistable Multivibrator
9.4 Schmitt Triggers
9.4.1 Calculation of the Upper Trip Point (V1)9.4.2 Calculation of the Lower Trip Point (V2)9.4.3 Methods to Eliminate Hysteresis in a Schmitt Trigger9.4.4 Applications of a Schmitt Trigger9.4.5 The Design of a Schmitt TriggerSummaryMultiple Choice QuestionsShort Answer QuestionsLong Answer QuestionsUnsolved Problems
10. Logic Gates
10.1 Introduction
10.2 Logic Gates
10.2.1 Simple Diode Gates10.2.2 Resistor–Transistor Logic Gates10.2.3 Diode−Transistor Logic Gates
10.3 Factors Defining the Performance of Logic Gates
10.4 Positive Logic, Negative Logic and Logic Circuit Conversion
10.4.1 Transistor–Transistor Logic Gates10.4.2 PMOS and NMOS Logic Gates10.4.3 Complementary MOSFET Logic Gates10.4.4 Interfacing of Logic GatesSummaryMultiple Choice QuestionsShort Answer QuestionsLong Answer QuestionsUnsolved Problems
11. Sampling Gates
11.1 Introduction
11.2 Unidirectional Diode Gates
11.2.1 Unidirectional Diode Gates to Transmit Positive Pulses11.2.2 Unidirectional Diode Gates11.2.3 A Unidirectional Diode Gate to Transmit Negative Pulses
11.3 Bidirectional Sampling Gates
11.3.1 Single-transistor Bidirectional Sampling Gates11.3.2 Two-transistor Bidirectional Sampling Gates11.3.3 A Two-transistor Bidirectional Sampling Gate that Reduces the Pedestal11.3.4 A Two-diode Bridge Type Bidirectional Sampling Gate that Eliminates the Pedestal11.3.5 Four-diode Gates11.3.6 Six-diode Gates
11.4 FET Sampling Gates
11.4.1 FET Series Gates11.4.2 FET Shunt Gates11.4.3 Op-amps as Sampling Gates
11.5 Applications of Sampling Gates
11.5.1 Chopper Stabilized Amplifiers11.5.2 Sampling Scopes11.5.3 MultiplexersSummaryMultiple Choice QuestionsShort Answer QuestionsLong Answer QuestionsUnsolved Problems
12. Voltage Sweep Generators
12.1 Introduction
12.2 Exponential Sweep Generators
12.2.1 A Voltage Sweep Generator Using a UJT12.2.2 Generation of Linear Sweep Using the CB Configuration
12.3 Improving Sweep Linearity
12.3.1 Miller Integrator Sweep Generators12.3.2 Bootstrap Sweep GeneratorsSummaryMultiple Choice QuestionsShort Answer QuestionsLong Answer QuestionsUnsolved Problems
13. Current Sweep Generators
13.1 Introduction
13.1.1 A Simple Current Sweep Generator13.1.2 Linearity Correction through Adjustment of the Driving Waveform
13.2 A Transistor Television Sweep Circuit
SummaryMultiple Choice QuestionsShort Answer QuestionsLong Answer QuestionsUnsolved Problems
14. Blocking Oscillators
14.1 Introduction
14.2 Monostable Blocking Oscillators
14.2.1 A Triggered Transistor Monostable Blocking Oscillator (Base Timing)14.2.2 A Triggered Transistor Blocking Oscillator (Emitter Timing)
14.3 Astable Blocking Oscillators
14.3.1 Diode-controlled Astable Blocking Oscillators14.3.2 RC-controlled Astable Blocking Oscillators14.3.3 Effect of Core Saturation on Pulse Width14.3.4 Applications of Blocking OscillatorsSummaryMultiple Choice QuestionsShort Answer QuestionsLong Answer QuestionsUnsolved Problems
15. Synchronization and Frequency Division
15.1 Introduction
15.2 Pulse Synchronization of Relaxation Devices
15.2.1 Frequency Division in a Sweep Circuit
15.3 Synchronization of Other Relaxation Circuits
15.3.1 Synchronization of Astable Blocking Oscillators15.3.2 Synchronization of Transistor Astable Multivibrators15.3.3 Synchronization with Division of an Astable Multivibrator by Applying Negative Pulses at both the Bases (B1 and B2)15.3.4 Positive Pulses Applied to B1 Through a Small Capacitor from a Low-impedance Source
15.4 A Monostable Multivibrator as a Divider
15.4.1 A Relaxation Divider that Eliminates Phase Jitter
15.5 Synchronization of a Sweep Circuit with Symmetrical Signals
15.5.1 Frequency Division with Symmetric Sync SignalsSummaryMultiple Choice QuestionsShort Answer QuestionsLong Answer QuestionsUnsolved Problems
16. Op-amps, 555 Timers and Negative Resistance Devices in Switching Applications
16.1 Introduction
16.2 Operational Amplifiers
16.2.1 Some Applications of an Operational Amplifier16.2.2 Monostable Multivibrators16.2.3 Astable Multivibrators16.2.4 An Astable Multivibrator Using an Operational Amplifier Without Zener Diodes16.2.5 A Schmitt Trigger Using an Operational Amplifier16.2.6 Miller Integrator Time-base Generators Using Operational Amplifiers16.2.7 A Bootstrap Time-base Generator Using an Operational Amplifier
16.3 555 Timer Applications
16.3.1 Monostable Circuits Using 555 Timers16.3.2 555 Astable Multivibrators16.3.3 Schmitt Trigger Circuits
16.4 Tunnel Diodes
16.4.1 A Monostable Circuit Using a Tunnel Diode16.4.2 An Astable Multivibrator Circuit Using a Tunnel Diode16.4.3 A Bistable Multivibrator Using a Tunnel Diode
16.5 A Four-layer p−n−p−n Diode
16.5.1 p−n−p−n Diode in a Monostable Circuit16.5.2 An Astable Multivibrator Using a p−n−p−n Diode (Voltage Sweep Generator)16.5.3 A Bistable Multivibrator Using a p−n−p−n Diode
16.6 Unijunction Transistors
16.6.1 An Astable Multivibrator Using a UJT16.6.2 A Bistable Multivibrator Using a UJTSummaryMultiple Choice QuestionsShort Answer QuestionsLong Answer QuestionsUnsolved Problems
17. Combinational Circuits: Implementation and Design
17.1 Introduction
17.2 Boolean Algebra
17.2.1 AND Operation17.2.2 OR Operation17.2.3 Complementation or Inversion
17.3 Realization of Boolean Functions Using Switches and Logic Gates
17.4 Theorems
17.4.1 Dual and Complementary Functions17.4.2 Boolean Algebraic Properties
17.5 Simplification of Boolean Functions
17.6 De Morgan’s Laws
17.7 Boolean Expressions in Sum of Products (SOP) Form and in Product of Sums (POS) Form
17.7.1 The Expansion of a Boolean Expression to the SOP Form17.7.2 The Expansion of a Boolean Expression to the POS Form17.7.3 Conversion from One Form to the Other
17.8 Universal Gates
17.8.1 Implementing a NOT Gate Using NAND Gates17.8.2 Implementing an AND Gate Using NAND Gates17.8.3 Implementing an OR Gate Using NAND Gates17.8.4 Implementing a NOT Gate Using NOR Gates17.8.5 Implementing an AND Gate Using NOR Gates17.8.6 Implementing an OR Gate Using NOR Gates17.8.7 The Exclusive OR Gate
17.9 The Realization of Logic Functions Using NAND Gates
17.9.1 The Realization of Logic Functions Using NOR Gates
17.10 Karnaugh Maps
SummaryMultiple Choice QuestionsShort Answer QuestionsLong Answer QuestionsUnsolved Problems
18. Sequential Circuits: Flip-flops and Counters
18.1 Introduction
18.2 Flip-flops
18.2.1 The Basic RS-latch18.2.2 The SR-latch Using NAND Gates18.2.3 Positive Pulse Triggered SR Flip-flops18.2.4 Clocked SR Flip-flops18.2.5 JK Flip-flops18.2.6 D Flip-flops18.2.7 T Flip-flops18.2.8 Master−Slave Flip-flops18.2.9 JK Master−Slave Flip-flops
18.3 Excitation Tables
18.3.1 Flip-flop Conversions
18.4 Counters
18.4.1 Asynchronous Counters18.4.2 Synchronous Counters
18.5 State Tables
18.5.1 State Diagrams
18.6 The Procedure to Design Counters
18.7 Modulus Counters
18.8 4-Bit Binary Up/Down Counters
SummaryMultiple Choice QuestionsShort Answer QuestionsLong Answer QuestionsUnsolved Problems
Appendix A: Conversion Equations and Laplace Transforms
Appendix B: Continuity Theorems in Network Analysis
Bibliography
Notes
Acknowledgements
Copyright

Content preview from Pulse and Digital Circuits

16.5 A FOUR-LAYER p–n–p–n DIODE

A p–n–p–n diode consists of four layers of silicon and these layers are doped alternately with p- and n-type impurities, as shown in Fig. 16.23(a). This can be redrawn as shown in Fig. 16.23(b). The p–n–p–n diode is represented schematically as shown in Fig. 16.23(c).

FIGURE 16.23(a) A p–n–p–n diode

FIGURE 16.23(b) The redrawn circuit of Fig. 16.23(a)

FIGURE 16.23(c) The schematic representation of p–n–p–n

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