Silicon Photonics: Fundamentals and Devices

8.7 CMOS and BiCMOS

The ability to realize a high-performance silicon-based photodetector in a production CMOS process is an attractive option for systems designers, but it is not easy to accomplish. This fact, in combination with the costs associated with optical packaging and the challenges of making high-performance CMOS receiver circuits, has challenged researchers and systems developers working to make fully integrated CMOS photoreceivers. The motivation and potential to produce such elements in CMOS have increased markedly as the speed of CMOS circuits has made them viable candidates for gigabit rate data communication. The integration of gigabit receivers became feasible in submicrometer CMOS 34.

Considering the CMOS vertical structure, three factors determine the responsivity. These factors are in the three square brackets in the following equation:

(8.40)

The first square bracket denotes optical attenuations A ≈ exp(−α_SiO2W_SiO2) and reflections R by the layers above silicon, where α_SiO2 and W_SiO2 are the absorption coefficient and thicknesses of insulating silicon dioxide layers that hold the metallization in CMOS.

The second brackets denote the optical absorption in a silicon-depleted layer of thickness W_D, where the Beer–Lambert law is assumed for the absorption coefficient α(λ) of silicon and L_diff is the diffusion length of minority carriers.

The last bracket denotes ...