book

Software Development for Embedded Multi-core Systems

Name: Software Development for Embedded Multi-core Systems
Author: Max Domeika
ISBN: 9780080558585

by Max Domeika

April 2011

Intermediate to advanced

440 pages

10h 2m

English

Newnes

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Copyright
Preface
Why This Book?Intended Audience
Acknowledgments
1. Introduction
1.1. Motivation1.2. The Advent of Multi-core Processors1.3. Multiprocessor Systems Are Not New1.4. Applications Will Need to be Multi-threaded1.5. Software Burden or Opportunity1.6. What is Embedded?1.7. What is Unique About Embedded?Chapter SummaryReferences
2. Basic System and Processor Architecture
2.1. Performance2.2. Brief History of Embedded Intel® Architecture Processors2.2.1. Intel® 186 Processor2.2.2. Intel386™ Processor2.2.2.1. 32-Bit Processor2.2.2.2. Protected Memory Model2.2.3. Intel486™ Processor2.2.3.1. Floating Point2.2.3.2. Cache Memory2.2.3.3. Pipelining2.2.4. Intel® Pentium Processor2.2.4.1. Superscalar Execution2.2.4.2. Performance Monitoring Counters2.2.5. The Intel® Pentium III Processor2.2.5.1. OOO Execution2.2.5.2. Streaming SIMD Extensions2.2.6. The Intel Pentium® 4 Processor2.2.6.1. Hyper-threading Technology2.2.7. The Intel Pentium® M Processor2.2.7.1. Power Utilization2.2.8. Dual-Core Intel Xeon® Processors LV and ULV and Dual-Core Intel® Xeon® Processor 5100 Series2.2.9. Intel® Core™ 2 Duo Processors for Embedded Computing2.2.9.1. Intel® 64 ISA2.2.10. Quad-Core Intel® Xeon® Processor 5300 Series2.3. Embedded Trends and Near Term Processor Impact2.3.1. Future 45 nm Embedded Processor2.3.2. Intel® Atom™ Processor Core2.3.3. Tolapai SOC Accelerator2.4. Tutorial on x86 Assembly Language2.4.1. X86 Assembly Basics2.4.2. Tip #1 – Focus on Small Regions2.4.3. Tip #2 – Quickly Identify Source and Destination2.4.4. Tip #3 – Learn Basic Registers and Memory References2.4.5. Tip #4 – Learn Basic Frequently Used Operations2.4.6. Tip #5 – Your Friendly Neighborhood Reference Manual2.4.7. Tip #6 – Beware of Compiler Optimization2.4.8. Tip #7 – Correlating Disassembly to Source2.4.9. Sample Assembly WalkthroughChapter SummaryRelated ReadingReferences
3. Multi-core Processors and Embedded
3.1. Motivation for Multi-core Processors3.2. Multi-core Processor Architecture3.2.1. Homogeneous Multi-core and Heterogeneous Multi-core3.2.2. Symmetric and Asymmetric Multi-core3.3. Benefits of Multi-core Processors in Embedded3.4. Embedded Market Segments and Multi-core Processors3.4.1. Wireless Telecommunications Infrastructure3.4.2. Industrial Control3.4.3. Federal (Military, Aerospace, Government)3.4.4. Enterprise Infrastructure Security3.4.5. In-vehicle Infotainment3.4.6. Interactive Clients3.4.7. Voice and Converged Communications3.4.8. Digital Security Surveillance3.4.9. Storage3.4.10. Medical3.5. Evaluating Performance of Multi-core Processors3.5.1. Single-core Performance Benchmark Suites3.5.2. Multi-core Performance Benchmarks3.5.3. Power Benchmarks3.5.4. Estimating Application Performance3.5.5. Characterizing Embedded System Performance3.5.6. Reviewing Benchmark DataChapter SummaryRelated ReadingReferences
4. Moving to Multi-core Intel Architecture
4.1. Migrating to Intel Architecture4.1.1. 32-Bit Versus 64-Bit Support4.1.1.1. 32-Bit x86 ISA4.1.1.2. Intel® 64 Instruction Set Architecture4.1.2. Endianness: Big to Little4.1.2.1. Endianness AssumptionEndian Neutral CodeQuickTransit * TechnologyBiEndian Technology4.1.3. BIOS and OSes Considerations4.1.3.1. Instruction Set Extension Support4.1.3.2. Symmetric Multiprocessing (SMP) Support4.1.3.3. Advanced Technologies (*Ts)4.1.3.4. Basic Input/Output System (BIOS)4.1.3.5. Extensible Firmware Interface (EFI)4.1.3.6. Desktop/Server OS4.1.3.7. Embedded Linux OS4.1.3.8. Embedded WindowsEmbedded Windows With a Real-time Extension4.1.3.9. Embedded OS4.1.3.10. Proprietary OS4.2. Enabling an SMP OS4.2.1. Basic MESI Protocol4.2.2. Device Driver and Kernel Programming Considerations4.3. Tools for Multi-core Processor Development4.3.1. OpenMP4.3.2. Automatic Parallelization4.3.3. Speculative Precomputation4.3.4. Thread Libraries4.3.4.1. Pthreads and Win32 Threads4.3.4.2. Intel® Threading Building Blocks4.3.4.3. Multi-threaded Domain-Specific Libraries4.3.4.4. C++ Thread Library4.3.5. Graphical Design Tools4.3.6. Debugger4.3.6.1. Multi-core Aware Debugging4.3.6.2. Thread Verification Tools4.3.7. Performance Analysis Tools4.3.7.1. Profiling4.3.7.2. Thread ProfilingChapter SummaryRelated ReadingReferences

5. Scalar Optimization and Usability
5.1. Compiler Optimizations5.1.1. General Optimizations5.1.2. Advanced Optimizations5.1.2.1. Automatic Vectorization5.1.2.2. Interprocedural Optimization5.1.2.3. Profile-guided Optimization5.1.3. Advanced Optimization Options5.1.4. Aiding Optimizations5.2. Optimization Process5.3. Usability5.3.1. Diagnostics5.3.2. Compatibility5.3.3. Compile Time5.3.4. PCH Files5.3.5. Parallel Build5.3.6. Code Size5.3.7. Code Coverage5.3.8. Optimization Effects on DebugChapter SummaryRelated ReadingReferences
6. Parallel Optimization Using Threads
6.1. Parallelism Primer6.1.1. Thread6.1.2. Decomposition6.1.3. Scalability6.1.4. Parallel Execution Limiters6.1.5. Threading Technology Requirements6.2. Threading Development Cycle6.2.1. Analysis6.2.1.1. Benchmark6.2.1.2. Tune for Serial Performance6.2.1.3. Collect an Execution Time Profile6.2.1.4. Collect a Call Graph Profile6.2.1.5. Flow Chart Hotspots6.2.1.6. Classify Most Frequently Executed Loops6.2.2. Design and Implementation6.2.2.1. Code Modifications6.2.3. Debug6.2.3.1. Basic Multi-threaded Debugging6.2.3.2. Thread-related BugsData RaceThread StallDeadlock6.2.3.3. Logging6.2.3.4. Finding Thread-related Bugs6.2.4. Tune6.2.4.1. Synchronization6.2.4.2. Memory HierarchyChapter SummaryRelated ReadingReferences
7. Case Study: Data Decomposition
7.1. A Medical Imaging Data Examiner7.1.1. Build Procedure7.1.2. Analysis7.1.2.1. Serial Optimization7.1.2.2. Benchmark7.1.2.3. Serial Optimization Results7.1.2.4. Execution Time Profile7.1.2.5. Collect a Call Graph Profile7.1.2.6. Flow Chart Hotspots7.1.2.7. Classify Most Frequently Executed Loops7.1.3. Design and Implement7.1.4. Debug7.1.4.1. AMIDE Loop #1 Debug7.1.4.2. Resolving Debug Issues7.1.5. TuneChapter SummaryReferences
8. Case Study: Functional Decomposition
8.1. Snort8.1.1. Application Overview8.1.2. Build Procedure8.2. Analysis8.2.1. Serial Optimization8.2.2. Benchmark8.2.3. Serial Optimization Results8.2.4. Execution Time Profile8.2.5. Call Graph Profile8.3. Design and Implement8.3.1. Threading Snort8.3.2. Code Modifications8.3.3. Flow Pinning8.3.4. Code Modifications for Flow Pinning8.4. Snort Debug8.4.1. Filtering Out False Errors8.5. TuneChapter SummaryReferences
9. Virtualization and Partitioning
9.1. Overview9.1.1. Preamble9.2. Virtualization and Partitioning9.2.1. VMM Architectures9.2.2. Virtualization’s Use Models and Benefits9.2.2.1. Workload Isolation9.2.2.2. Workload Consolidation9.2.2.3. Workload Migration9.2.2.4. Clustering Over SMP ... and More9.2.2.5. Platform Management9.2.3. Motivation in Telecom/Embedded9.2.3.1. Business Considerations9.2.3.2. Real-Time OS Support9.2.3.3. High Availability9.2.3.4. Break Through the Performance Scaling Barrier9.3. Techniques and Design Considerations9.3.1. Virtualization’s Challenges on x86 Processors9.3.1.1. Privilege Management9.3.1.2. Memory Management9.3.1.3. Interrupts and Exceptions Management9.3.1.4. Missing Support and Future Roadmap9.4. Telecom Use Case of Virtualization9.4.1. Setup and Configuration BKMs9.4.2. Compute and Network I/O PerformanceChapter SummaryRelated ReadingReferences
10. Getting Ready for Low Power Intel Architecture
10.1. Architecture10.1.1. In-order ExecutionMiscellaneous Techniques for Energy Efficient Software10.2. Debugging Embedded Systems10.2.1. Brief History of Embedded Systems Debugging10.2.2. JTAG and Future Trends in Embedded Debugging10.2.3. Hardware Platform Bringup10.2.4. OS and Device Driver Debugging10.2.4.1. Case Study: OS Kernel Debugging10.2.4.2. Case Study: Debugging Services and Drivers10.2.5. Application Debugging10.2.6. Considerations for Multi-core Debugging10.2.6.1. JTAG10.2.6.2. Debug Handler/ApplicationChapter SummaryReferences
11. Summary, Trends, and Conclusions
11.1. Trends11.1.1. Processor Trends11.1.2. Software Challenges11.1.2.1. Intel® QuickAssist Technology11.1.2.2. Multicore Association Communication API (MCAPI)11.1.2.3. Software Transactional Memory11.1.3. Bandwidth Challenges11.2. Conclusions
Appendix A
Glossary

Content preview from Software Development for Embedded Multi-core Systems

Chapter 5. Scalar Optimization and Usability

Key Points

Before beginning a parallel optimization project, make sure a good effort at scalar performance optimization has already been invested.
A compiler that targets your processor and features advanced optimizations such as automatic vectorization, interprocedural optimization, and profile-guided optimization can substantially improve performance of your application.
Applying usability features of your compiler such as those aiding compatibility, compile time, and code size, can substantially improve development efficiency.

As discussed in Chapter 4, a variety of tools are available to help with multi-core software development. After reading that chapter you may be led to believe the next step is ...

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Software Development for Embedded Multi-core Systems

by Max Domeika

Chapter 5. Scalar Optimization and Usability

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