Clocking of precharge circuits requires the use of multiple clock phases. In the simplest case, two-clock phases could be used and this is often referred to as “traditional two-phase” design. In a more general case, one could use more than one-clock phase, such as four-clock phases [6], but this is beyond the scope of this book.

In two-phase clocking, we need to have two clocks. The chip can generate two clocks at the phase locked loop (PLL) and distribute both clock networks to all chip components. This requires quite a lot of overhead, so in many cases, designers choose to route just one clock and generate the complement at a more local level.

Let us now establish a naming convention for our clocks. The first phase will be known as ...

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