Synchronous Precharge Logic

7

Clocked Set–Reset Latches

This chapter describes how a CSR latch works as well as the timing aspects related to these latches. The CSR latch is also known as the dynamic latch, zero keeper, glitch latch, set dominant latch, C²MOS latch, and dynamic to static converter.

The monotonic properties of precharge circuits can be exploited to simplify the required latch on the output of such a path [29]. This is shown in Figure 7.1. The figure shows a chain of domino gates enabled by clock1, a latch, and the first stage of a clock2 domino chain. At the end of the evaluate phase, when clock1 falls, the value on signal B must be held steady while the clock1 chain precharges. The latch is simplified (compared to a standard four-transistor latch), by observing ...