Synchronous Precharge Logic

8

Layout Considerations

Traditionally, precharged gates could be optimized to minimize delay. The pull-down delay could be reduced by progressively reducing the width of transistors moving up a stack [9]. By keeping the total device area constant and sizing each device to be 25% smaller than the one below it, a 20% reduction in delay can be achieved for a six-input NAND gates [9]. Even if the area is not preserved (we keep the bottom device the same size and simply move up the stack, reducing the size of each device), there can be some reduction in delay. Is should be noted that in submicron technologies, the reduction in delay is only 2–4% [10].

Figure 8.1 shows an example layout with such “tapered” devices. Looking at this layout, it is obvious ...