Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems

10.4 SELF-TIMED CIRCUITS

Instead of synthesizing synchronous circuits, an alternative solution, especially in the case of large circuits, is self-timing. As a matter of fact, the synchronous approach has some pitfalls:

• It assumes that all clock events happen at the same time over the complete circuit; this is not the case in reality (clock skew).
• The simultaneous transition of all clock signals might generate noise problems.

  

  Figure 10.7 Pipelined 128-bit adder.

• The latency and throughput of the circuit are linked to the worst-case delay of the slowest element instead of the average case.

As a generic example, consider the pipelined circuit of Figure 10.8. To each block, for example number i, are associated a maximum delay t_max(i) and an average one t_av(i). The latency and throughput of the circuit of Figure 10.8 are equal to n.T_clk and 1/T_clk, respectively where T_clk > max{t_max(0), t_max(1), …, t_max(n − 1)}, that is,

Figure 10.8 Generic pipelined circuit.

A self-timed version of the same circuit is shown in Figure 10.9. The control is based on a request/acknowledge handshaking protocol:

• the Req input of block 0 is raised; if block 0 is free the data is registered (en), and the ...