## 15.1 OPERATIONS IN Z_{m}

### 15.1.1 Adders and Subtractors

The structure of a base-*B* modulo *m* adder is shown in Figure 15.1. It is based on Algorithm 8.2. Its cost is equal to

**Figure 15.1** Modulo *m* adder.

If every adder is a ripple-carry adder made up of full-adder cells, then its computation time is equal to

The structure of a modulo *m* subtractor is shown in Figure 15.2. It is based on Algorithm 8.4. Its cost and computation time are practically the same as in the case of the modulo *m* adder.

If every *n*-digit adder is a ripple-carry adder made up of full-adder cells, then its computation time is equal to

**Example 15.1** (Complete VHDL source code available.) Generate VHDL models of binary (*B* = 2) modulo *m* adders and subtractors:

entity mod_adder is
port (
x, y: in std_logic_vector(n-1 downto 0);
z: out std_logic_vector(n-1 downto 0) ); end mod_adder; architecture circuit of mod_adder is signal z1, z2: std_logic_vector(n-1 downto 0); signal c1, c2: std_logic; signal long_x, long_y, long_result1, ...