Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits

8

Circuit Topology-Based Test Pattern Generation for Small-Delay Defects

K. Goel Sandeep and Chakrabarty Krish

8.1 Introduction

8.2 Circuit Topology-Based Fault Selection

8.3 SDD Pattern Generation

8.4 Experimental Results and Analysis

8.4.1 Delay Test Coverage

8.4.2 Number of Unique Long Paths

8.4.3 Length of Longest Path

8.4.4 Number of Unique SDDs

8.4.5 Random Fault Injection and Detection

8.5 Conclusion

References

8.1 Introduction

Advances in design methods and process technology are continuing to push the envelope for integrated circuits. The use of advanced process technology brings forward several design and test challenges. In addition to manufacturing defects such as resistive opens/bridges, design-related issues such as process ...