The ESD Handbook

HLatchup Design Rules

H.1 Latchup Design Rule Checking (DRC)

Electrical overstress (EOS) can lead to latchup in semiconductor components and systems. Latchup tolerance can be minimized through semiconductor chip process technology, design layout, circuit design and system design. Electronic design automation (EDA) can be used to check and verify latchup robustness of a component on a semiconductor chip level.

Latchup design rule checking (DRC) is important to avoid latchup concerns in semiconductor components. In the 1980s, semiconductor corporations and foundries had few means of using EDA tools to check and verify for latchup. The first latchup sections were being placed in technology design manuals in the mid-1980s.

Today, latchup design rule checking (DRC) is included within design checking and verification. Latchup can occur in semiconductor devices in the following categories:

• Latchup between devices within a common circuit.
• Latchup between devices between different circuits.
• I/O circuit to I/O circuit latchup.
• I/O circuit to electrostatic discharge (ESD) circuit latchup.
• I/O circuit to core circuit latchup.
• Domain-to-domain latchup.

To address these issues, the solutions from a layout and design perspective can be achieved through physical spacing, separation of domains, and placement of guard rings to avoid formation of a parasitic pnpn that can lead to latchup. Latchup DRC check categories include the following (Figure 10.6):

• Placement of connections to power rails ...