An Overview of the 486 FSB

Address/Data Bus Structure

The 486DX processor implemented the same address/data bus structure as that found on the 386DX processor (see Figure 5-2 on page 44).

On a Cache Miss, an Entire Line Must Be Fetched

When the Instruction Prefetcher or the Execution Unit submits a memory access request to the internal cache, the line that contains the critical data (i.e., the requested data) may not be in the cache. In this event, the processor uses the FSB to fetch the line containing the critical data from memory. The cache line size for the 486 processor was 16 bytes (four dwords).If the 486 FSB were implemented in the same manner as the 386DX processor, the processor would have to perform four separate dword reads from memory ...

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