The Processor's State After Reset
The assertion of the processor's reset input has the effects indicated in Table 37-1 on page 878.
Table 37-1. Effects of Reset on the CPU
|L3 Cache||If the processor implements an L3 Cache, all entries in the L3 Cache are invalidated.|
|L2 Cache||All entries in the L2 Cache are invalidated.|
|Trace Cache||All entries in the Trace Cache are invalidated.|
|L1 Data Cache||All entries in the L1 Data Cache are invalidated.|
|Branch Target Buffers (BTBs)||All entries in the BTBs are invalidated, causing all initial branches to be predicted by the static, rather than dynamic, branch prediction units. For additional information, refer to “The Front-End BTB” on page 910, “The Static Branch Predictor” on page 911, and “The Trace Cache ...|
Get The Unabridged Pentium 4 IA32 Processor Genealogy now with O’Reilly online learning.
O’Reilly members experience live online training, plus books, videos, and digital content from 200+ publishers.