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The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

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The Front-End Pipeline Stages

Refer to Figure 38-4 on page 904. These are the stages that fetch legacy IA32 instructions from memory, decodes them into μops, caches them in the Trace Cache, queues them up, and feeds them to the μop pipeline (pictured in Figure 38-3 and Figure 38-1). As noted in Figure 38-2, the L1 Data Cache is not shown because the emphasis in this discussion is on the fetching, decoding and execution of instructions. A detailed description of the L1 Data Cache can be found in “The Pentium® 4 Caches” on page 1009.

Figure 38-4. The Code Fetch Is Initiated

The sections that follow describe the various elements ...

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