The Unabridged Pentium 4 IA32 Processor Genealogy

The Signals

Table 55-1 on page 1314 provides a description of each of the processor pins that were not covered in the chapters on the Pentium® 4 FSB protocol.

Table 55-1. Miscellaneous Signals

Signal(s)	Description
A20M#	Address bit 20 Mask. Input. See “A20 Mask” on page 419.
BINIT#	Bus Initialization. Input/output. BINIT# is asserted by an agent when the FSB cannot be reliably used for future transactions. As an example, if an agent's IOQ is corrupted, it can no longer reliably track transactions and therefore cannot reliably interact with the FSB at the appropriate times. How a processor uses BINIT# is set up as follows: The ability of a processor to assert BINIT# can be configured at power-up time (in MSR_EBC_SOFT_POWERON; see “Program-Accessible ...