Figures

1-1 The Bare Bones Processor Is an Instruction Fetch, Decode, Execution Engine 13

1-2 Processor Actions at Startup 14

1-3 Typical PC System Board Layout and Block Diagram 19

2-1 Task/OS Relationship 26

5-1 386 Internal Architecture 41

5-2 386DX FSB 44

5-3 386 Register Set 45

5-4 386 Control Register 0 (CR0) 47

5-5 Control Register 2 (CR2) 47

5-6 386 Control Register 3 (CR3) 48

5-7 386 Extended Flags Register (EFlags) 49

5-8 The General Purpose Registers (GPRs) 54

5-9 The Segment Registers 56

5-10 Segment Registers Identify Memory Areas Associated with Executing Program 56

5-11 EIP Register 57

5-12 Task State Segment (TSS) 59

5-13 The Task Register Identifies the TSS Associated with the Currently Executing Tasks 60

5-14 GDTR and LDTR 61

5-15 The IDT in ...

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