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Verilog® HDL: A Guide to Digital Design and Synthesis, Second Edition

Name: Verilog® HDL: A Guide to Digital Design and Synthesis, Second Edition
Author: Samir Palnitkar
ISBN: 9780130449115

by Samir Palnitkar

February 2003

Intermediate to advanced

496 pages

8h 16m

English

Pearson

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Copyright
Dedication
About the Author
List of Figures
List of Tables
List of Examples
Foreword
Preface
Who Should Use This BookHow This Book Is OrganizedConventions Used in This Book
Acknowledgments
1. Basic Verilog Topics
1. Overview of Digital Design with Verilog HDL
1.1. Evolution of Computer-Aided Digital Design1.2. Emergence of HDLs1.3. Typical Design Flow1.4. Importance of HDLs1.5. Popularity of Verilog HDL1.6. Trends in HDLs

2. Hierarchical Modeling Concepts
2.1. Design Methodologies2.2. 4-bit Ripple Carry Counter2.3. Modules2.4. Instances2.5. Components of a Simulation2.6. Example2.6.1. Design Block2.6.2. Stimulus Block2.7. Summary2.8. Exercises
3. Basic Concepts
3.1. Lexical Conventions3.1.1. Whitespace3.1.2. Comments3.1.3. Operators3.1.4. Number SpecificationSized numbersUnsized numbersX or Z valuesNegative numbersUnderscore characters and question marks3.1.5. Strings3.1.6. Identifiers and Keywords3.1.7. Escaped Identifiers3.2. Data Types3.2.1. Value Set3.2.2. Nets3.2.3. Registers3.2.4. VectorsVector Part SelectVariable Vector Part Select3.2.5. Integer , Real, and Time Register Data TypesIntegerRealTime3.2.6. Arrays3.2.7. Memories3.2.8. Parameters3.2.9. Strings3.3. System Tasks and Compiler Directives3.3.1. System TasksDisplaying informationMonitoring informationStopping and finishing in a simulation3.3.2. Compiler Directives`define`include3.4. Summary3.5. Exercises
4. Modules and Ports
4.1. Modules4.2. Ports4.2.1. List of Ports4.2.2. Port Declaration4.2.3. Port Connection RulesInputsOutputsInoutsWidth matchingUnconnected portsExample of illegal port connection4.2.4. Connecting Ports to External SignalsConnecting by ordered listConnecting ports by name4.3. Hierarchical Names4.4. Summary4.5. Exercises
5. Gate-Level Modeling
5.1. Gate Types5.1.1. And/Or Gates5.1.2. Buf/Not GatesBufif/notif5.1.3. Array of Instances5.1.4. ExamplesGate-level multiplexer4-bit Ripple Carry Full Adder5.2. Gate Delays5.2.1. Rise, Fall, and Turn-off DelaysRise delayFall delayTurn-off delay5.2.2. Min/Typ/Max ValuesMin valueTyp valMax value5.2.3. Delay Example5.3. Summary5.4. Exercises
6. Dataflow Modeling
6.1. Continuous Assignments6.1.1. Implicit Continuous Assignment6.1.2. Implicit Net Declaration6.2. Delays6.2.1. Regular Assignment Delay6.2.2. Implicit Continuous Assignment Delay6.2.3. Net Declaration Delay6.3. Expressions, Operators, and Operands6.3.1. Expressions6.3.2. Operands6.3.3. Operators6.4. Operator Types6.4.1. Arithmetic OperatorsBinary operatorsUnary operators6.4.2. Logical Operators6.4.3. Relational Operators6.4.4. Equality Operators6.4.5. Bitwise Operators6.4.6. Reduction Operators6.4.7. Shift Operators6.4.8. Concatenation Operator6.4.9. Replication Operator6.4.10. Conditional Operator6.4.11. Operator Precedence6.5. Examples6.5.1. 4-to-1 MultiplexerMethod 1: logic equationMethod 2: conditional operator6.5.2. 4-bit Full AdderMethod 1: dataflow operatorsMethod 2: full adder with carry lookahead6.5.3. Ripple Counter6.6. Summary6.7. Exercises
7. Behavioral Modeling
7.1. Structured Procedures7.1.1. initial StatementCombined Variable Declaration and InitializationCombined Port/Data Declaration and InitializationCombined ANSI C Style Port Declaration and Initialization7.1.2. always Statement7.2. Procedural Assignments7.2.1. Blocking Assignments7.2.2. Nonblocking AssignmentsApplication of nonblocking assignments7.3. Timing Controls7.3.1. Delay-Based Timing ControlRegular delay controlIntra-assignment delay controlZero delay control7.3.2. Event-Based Timing ControlRegular event controlNamed event controlEvent OR Control7.3.3. Level-Sensitive Timing Control7.4. Conditional Statements7.5. Multiway Branching7.5.1. case Statement7.5.2. casex, casez Keywords7.6. Loops7.6.1. While Loop7.6.2. For Loop7.6.3. Repeat Loop7.6.4. Forever loop7.7. Sequential and Parallel Blocks7.7.1. Block TypesSequential blocksParallel blocks7.7.2. Special Features of BlocksNested blocksNamed blocksDisabling named blocks7.8. Generate Blocks7.8.1. Generate Loop7.8.2. Generate Conditional7.8.3. Generate Case7.9. Examples7.9.1. 4-to-1 Multiplexer7.9.2. 4-bit Counter7.9.3. Traffic Signal ControllerSpecificationVerilog descriptionStimulus7.10. Summary7.11. Exercises
8. Tasks and Functions
8.1. Differences between Tasks and Functions8.2. Tasks8.2.1. Task Declaration and Invocation8.2.2. Task ExamplesUse of input and output argumentsAsymmetric Sequence Generator8.2.3. Automatic (Re-entrant) Tasks8.3. Functions8.3.1. Function Declaration and Invocation8.3.2. Function ExamplesParity calculationLeft/right shifter8.3.3. Automatic (Recursive) Functions8.3.4. Constant Functions8.3.5. Signed Functions8.4. Summary8.5. Exercises
9. Useful Modeling Techniques
9.1. Procedural Continuous Assignments9.1.1. assign and deassign9.1.2. force and releaseforce and release on registersforce and release on nets9.2. Overriding Parameters9.2.1. defparam Statement9.2.2. Module_Instance Parameter Values9.3. Conditional Compilation and Execution9.3.1. Conditional Compilation9.3.2. Conditional Execution9.4. Time Scales9.5. Useful System Tasks9.5.1. File OutputOpening a fileWriting to filesClosing files9.5.2. Displaying Hierarchy9.5.3. Strobing9.5.4. Random Number Generation9.5.5. Initializing Memory from File9.5.6. Value Change Dump File9.6. Summary9.7. Exercises
2. Advanced VerilogTopics
10. Timing and Delays
10.1. Types of Delay Models10.1.1. Distributed Delay10.1.2. Lumped Delay10.1.3. Pin-to-Pin Delays10.2. Path Delay Modeling10.2.1. Specify Blocks10.2.2. Inside Specify BlocksParallel connectionFull connectionEdge-Sensitive Pathsspecparam statementsConditional path delaysRise, fall, and turn-off delaysMin, max, and typical delaysHandling x transitions10.3. Timing Checks10.3.1. $setup and $hold Checks$setup task$hold task10.3.2. $width Check10.4. Delay Back-Annotation10.5. Summary10.6. Exercises
11. Switch-Level Modeling
11.1. Switch-Modeling Elements11.1.1. MOS Switches11.1.2. CMOS Switches11.1.3. Bidirectional Switches11.1.4. Power and Ground11.1.5. Resistive Switches11.1.6. Delay Specification on SwitchesMOS and CMOS switchesBidirectional pass switchesSpecify blocks11.2. Examples11.2.1. CMOS Nor Gate11.2.2. 2-to-1 Multiplexer11.2.3. Simple CMOS Latch11.3. Summary11.4. Exercises
12. User-Defined Primitives
12.1. UDP basics12.1.1. Parts of UDP Definition12.1.2. UDP Rules12.2. Combinational UDPs12.2.1. Combinational UDP Definition12.2.2. State Table Entries12.2.3. Shorthand Notation for Don't Cares12.2.4. Instantiating UDP Primitives12.2.5. Example of a Combinational UDP12.3. Sequential UDPs12.3.1. Level-Sensitive Sequential UDPs12.3.2. Edge-Sensitive Sequential UDPs12.3.3. Example of a Sequential UDP12.4. UDP Table Shorthand Symbols12.5. Guidelines for UDP Design12.6. Summary12.7. Exercises
13. Programming Language Interface
13.1. Uses of PLI13.2. Linking and Invocation of PLI Tasks13.2.1. Linking PLI Tasks13.2.2. Invoking PLI Tasks13.2.3. General Flow of PLI Task Addition and Invocation13.3. Internal Data Representation13.4. PLI Library Routines13.4.1. Access RoutinesMechanics of access routinesTypes of access routinesExamples of access routines13.4.2. Utility RoutinesMechanics of utility routinesTypes of utility routinesExample of utility routines13.5. Summary13.6. Exercises
14. Logic Synthesis with Verilog HDL
14.1. What Is Logic Synthesis?14.2. Impact of Logic Synthesis14.3. Verilog HDL Synthesis14.3.1. Verilog Constructs14.3.2. Verilog Operators14.3.3. Interpretation of a Few Verilog ConstructsThe assign statementThe if-else statementThe case statementfor loopsThe function statement14.4. Synthesis Design Flow14.4.1. RTL to GatesRTL descriptionTranslationUnoptimized intermediate representationLogic optimizationTechnology mapping and optimizationTechnology libraryDesign constraintsOptimized gate-level description14.4.2. An Example of RTL-to-GatesDesign specificationRTL descriptionTechnology libraryDesign constraintsLogic synthesisFinal, Optimized, Gate-Level DescriptionIC Fabrication14.5. Verification of Gate-Level Netlist14.5.1. Functional VerificationTiming verification14.6. Modeling Tips for Logic Synthesis14.6.1. Verilog Coding StyleUse meaningful names for signals and variablesAvoid mixing positive and negative edge-triggered flipflopsUse basic building blocks vs. use continuous assign statementsInstantiate multiplexers vs. Use if-else or case statementsUse parentheses to optimize logic structureUse arithmetic operators *, /, and % vs. Design building blocksBe careful with multiple assignments to the same variableDefine if-else or case statements explicitly14.6.2. Design PartitioningHorizontal partitioningVertical PartitioningParallelizing design structure14.6.3. Design Constraint Specification14.7. Example of Sequential Circuit Synthesis14.7.1. Design Specification14.7.2. Circuit Requirements14.7.3. Finite State Machine (FSM)14.7.4. Verilog Description14.7.5. Technology Library14.7.6. Design Constraints14.7.7. Logic Synthesis14.7.8. Optimized Gate-Level Netlist14.7.9. Verification14.8. Summary14.9. Exercises
15. Advanced Verification Techniques
15.1. Traditional Verification Flow15.1.1. Architectural Modeling15.1.2. Functional Verification Environment15.1.3. SimulationSoftware SimulationHardware AccelerationHardware Emulation15.1.4. Analysis15.1.5. CoverageStructural CoverageFunctional Coverage15.2. Assertion Checking15.3. Formal Verification15.3.1. Semi-formal Verification15.3.2. Equivalence Checking15.4. Summary
3. Appendices
A. Strength Modeling and Advanced Net Definitions
A.1. Strength LevelsA.2. Signal ContentionA.2.1. Multiple Signals with Same Value and Different StrengthA.2.2. Multiple Signals with Opposite Value and Same StrengthA.3. Advanced Net TypesA.3.1. triA.3.2. triregA.3.3. tri0 and tri1A.3.4. supply0 and supply1A.3.5. wor, wand, trior, and triand
B. List of PLI Routines
B.1. ConventionsB.2. Access RoutinesB.2.1. Handle RoutinesB.2.2. Next RoutinesB.2.3. Value Change Link (VCL) RoutinesB.2.4. Fetch RoutinesB.2.5. Utility Access RoutinesB.2.6. Modify RoutinesB.3. Utility (tf_) RoutinesB.3.1. Get Calling Task/Function InformationB.3.2. Get Argument List InformationB.3.3. Get Parameter ValuesB.3.4. Put Parameter ValueB.3.5. Monitor Parameter Value ChangesB.3.6. Synchronize TasksB.3.7. Long ArithmeticB.3.8. Display MessagesB.3.9. Miscellaneous Utility RoutinesB.3.10. Housekeeping Tasks
C. List of Keywords, System Tasks, and Compiler Directives
C.1. KeywordsC.2. System Tasks and FunctionsC.3. Compiler Directives
D. Formal Syntax Definition
D.1. Source TextD.1.1. Library Source TextD.1.2. Configuration Source TextD.1.3. Module and Primitive Source TextD.1.4. Module Parameters and PortsD.1.5. Module ItemsD.2. DeclarationsD.2.1. Declaration TypesModule parameter declarationsPort declarationsType declarationsD.2.2. Declaration Data TypesNet and variable typesStrengthsDelaysD.2.3. Declaration ListsD.2.4. Declaration AssignmentsD.2.5. Declaration RangesD.2.6. Function DeclarationsD.2.7. Task DeclarationsD.2.8. Block Item DeclarationsD.3. Primitive InstancesD.3.1. Primitive Instantiation and InstancesD.3.2. Primitive StrengthsD.3.3. Primitive TerminalsD.3.4. Primitive Gate and Switch TypesD.4. Module and Generated InstantiationD.4.1. Module InstantiationD.4.2. Generated InstantiationD.5. UDP Declaration and InstantiationD.5.1. UDP DeclarationD.5.2. UDP PortsD.5.3. UDP BodyD.5.4. UDP InstantiationD.6. Behavioral StatementsD.6.1. Continuous Assignment StatementsD.6.2. Procedural Blocks and AssignmentsD.6.3. Parallel and Sequential BlocksD.6.4. StatementsD.6.5. Timing Control StatementsD.6.6. Conditional StatementsD.6.7. Case StatementsD.6.8. Looping StatementsD.6.9. Task Enable StatementsD.7. Specify SectionD.7.1. Specify Block DeclarationD.7.2. Specify Path DeclarationsD.7.3. Specify Block TerminalsD.7.4. Specify Path DelaysD.7.5. System Timing ChecksSystem timing check commandsSystem timing check command argumentsSystem timing check event definitionsD.8. ExpressionsD.8.1. ConcatenationsD.8.2. Function callsD.8.3. ExpressionsD.8.4. PrimariesD.8.5. Expression Left-Side ValuesD.8.6. OperatorsD.8.7. NumbersD.8.8. StringsD.9. GeneralD.9.1. AttributesD.9.2. CommentsD.9.3. IdentifiersD.9.4. Identifier BranchesD.9.5. WhitespaceEndnotes
E. Verilog Tidbits
Origins of Verilog HDLInterpreted, Compiled, Native Compiled SimulatorsEvent-Driven Simulation, Oblivious SimulationCycle-Based SimulationFault SimulationGeneral Verilog Web sitesArchitectural Modeling ToolsHigh-Level Verification LanguagesSimulation ToolsHardware Acceleration ToolsIn-Circuit Emulation ToolsCoverage ToolsAssertion Checking ToolsEquivalence Checking ToolsFormal Verification Tools
F. Verilog Examples
F.1. Synthesizable FIFO ModelInput portsOutput portsF.2. Behavioral DRAM ModelInput portsInout ports
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Content preview from Verilog® HDL: A Guide to Digital Design and Synthesis, Second Edition

Chapter 4. Modules and Ports

In the previous chapters, we acquired an understanding of the fundamental hierarchical modeling concepts, basic conventions, and Verilog constructs. In this chapter, we take a closer look at modules and ports from the Verilog language point of view.

Learning Objectives

Identify the components of a Verilog module definition, such as module names, port lists, parameters, variable declarations, dataflow statements, behavioral statements, instantiation of other modules, and tasks or functions.
Understand how to define the port list for a module and declare it in Verilog.
Describe the port connection rules in a module instantiation.
Understand how to connect ports to external signals, by ordered list, and by name.
Explain hierarchical ...

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Verilog® HDL: A Guide to Digital Design and Synthesis, Second Edition

by Samir Palnitkar

Chapter 4. Modules and Ports

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