book

VHDL: Programming by Example

Name: VHDL: Programming by Example
Author: Douglas Perry
ISBN: 9780071400701

by Douglas Perry

May 2002

Intermediate to advanced

476 pages

11h 30m

English

McGraw-Hill

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Cover
VHDL: Programming by Example, Fourth Edition
Copyright Page
CD Content
Dedication
CONTENTS
Foreword
Preface
Acknowledgments
Chapter 1 Introduction to VHDL
VHDL TermsDescribing Hardware in VHDLEntityArchitecturesConcurrent Signal AssignmentEvent SchedulingStatement ConcurrencyStructural DesignsSequential BehaviorProcess StatementsProcess Declarative RegionProcess Statement PartProcess ExecutionSequential StatementsArchitecture SelectionConfiguration StatementsPower of Configurations

Chapter 2 Behavioral Modeling
Introduction to Behavioral ModelingTransport Versus Inertial DelayInertial DelayTransport DelayInertial Delay ModelTransport Delay ModelSimulation DeltasDriversDriver CreationBad Multiple Driver ModelGenericsBlock StatementsGuarded Blocks
Chapter 3 Sequential Processing
Process StatementSensitivity ListProcess ExampleSignal Assignment Versus Variable AssignmentIncorrect Mux ExampleCorrect Mux ExampleSequential StatementsIF StatementsCASE StatementsLOOP StatementsNEXT StatementEXIT StatementASSERT StatementAssertion BNFWAIT StatementsWAIT ON SignalWAIT UNTIL ExpressionWAIT FOR time_expressionMultiple WAIT ConditionsWAIT Time-OutSensitivity List Versus WAIT StatementConcurrent Assignment ProblemPassive Processes
Chapter 4 Data Types
Object TypesSignalVariablesConstantsData TypesScalar TypesComposite TypesIncomplete TypesFile TypesFile Type CaveatsSubtypes
Chapter 5 Subprograms and Packages
SubprogramsFunctionConversion FunctionsResolution FunctionsProceduresPackagesPackage DeclarationDeferred ConstantsSubprogram DeclarationPackage Body
Chapter 6 Predefined Attributes
Value Kind AttributesValue Type AttributesValue Array AttributesValue Block AttributesFunction Kind AttributesFunction Type AttributesFunction Array AttributesFunction Signal AttributesAttributes ’EVENT and ’LAST_VALUEAttribute ’LAST_EVENTAttribute ’ACTIVE and ’LAST_ACTIVESignal Kind AttributesAttribute ’DELAYEDAttribute ’STABLEAttribute ’QUIETAttribute ’TRANSACTIONType Kind AttributesRange Kind Attributes
Chapter 7 Configurations
Default ConfigurationsComponent ConfigurationsLower-Level ConfigurationsEntity-Architecture Pair ConfigurationPort MapsMapping Library EntitiesGenerics in ConfigurationsGeneric Value Specification in ArchitectureGeneric Specifications in ConfigurationsBoard-Socket-Chip AnalogyBlock ConfigurationsArchitecture Configurations
Chapter 8 Advanced Topics
OverloadingSubprogram OverloadingOverloading OperatorsAliasesQualified ExpressionsUser-Defined AttributesGenerate StatementsIrregular Generate StatementTextIO
Chapter 9 Synthesis
Register Transfer Level DescriptionConstraintsTiming ConstraintsClock ConstraintsAttributesLoadDriveArrival TimeTechnology LibrariesSynthesisTranslationBoolean OptimizationFlatteningFactoringMapping to Gates
Chapter 10 VHDL Synthesis
Simple Gate — Concurrent AssignmentIF Control Flow StatementsCase Control Flow StatementsSimple Sequential StatementsAsynchronous ResetAsynchronous Preset and ClearMore Complex Sequential StatementsFour-Bit ShifterState Machine Example
Chapter 11 High Level Design Flow
RTL SimulationVHDL SynthesisFunctional Gate-Level VerificationPlace and RoutePost Layout Timing SimulationStatic Timing
Chapter 12 Top-Level System Design
CPU DesignTop-Level System OperationInstructionsSample Instruction RepresentationCPU Top-Level DesignBlock Copy Operation
Chapter 13 CPU: Synthesis Description
ALUCompControlRegRegarrayShiftTrireg
Chapter 14 CPU: RTL Simulation
TestbenchesKinds of TestbenchesStimulus OnlyFull TestbenchSimulator SpecificHybrid TestbenchesFast TestbenchCPU Simulation
Chapter 15 CPU Design: Synthesis Results
Chapter 16 Place and Route
Place and Route ProcessPlacing and Routing the DeviceSetting up a project
Chapter 17 CPU: VITAL Simulation
VITAL LibraryVITAL Simulation Process OverviewVITAL ImplementationSimple VITAL ModelVITAL ArchitectureWire Delay SectionFlip-Flop ExampleSDF FileVITAL SimulationBack-Annotated Simulation
Chapter 18 At Speed Debugging Techniques
InstrumentorDebuggerDebug CPU DesignCreate ProjectSpecify Top-Level ParametersSpecify Project ParametersInstrument SignalsWrite Instrumented DesignImplement New DesignStart DebugEnable BreakpointTrigger PositionWaveform DisplaySet WatchpointComplex Triggers
Appendix A Standard Logic Package
Appendix B VHDL Reference Tables
Appendix C Reading VHDL BNF
Appendix D VHDL93 Updates
AliasAttribute ChangesBit String LiteralDELAY_LENGTH SubtypeDirect InstantiationExtended IdentifiersFile OperationsForeign InterfaceGenerate Statement ChangesGlobally Static AssignmentGroupsIncremental BindingPostponed ProcessPure and Impure FunctionsPulse RejectReport StatementShared VariablesShift OperatorsSLL — shift left logicalSRL — shift right logicalSLA — shift left arithmeticSRA — shift right arithmeticROL — rotate leftROR — rotate rightSyntax ConsistencyUnaffectedXNOR Operator
Index
About the Author
For Download

Content preview from VHDL: Programming by Example

CHAPTER 14 CPU: RTL Simulation

In this chapter, a VHDL simulator is used to verify the functionality of the CPU VHDL RTL description. The VHDL RTL description of the CPU is simulated with a standard VHDL simulator to verify that the description is correct.

A simulator needs two inputs: the description of the design and stimulus to drive the design. Sometimes designs are self-stimulating and do not need any external stimulus, but in most cases, VHDL designers use a VHDL testbench of one kind or another to drive the design being tested. The structure of the design looks like Figure 14-1.

Figure 14-1Top-Level Design Structure.

The top-level design ...

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VHDL: Programming by Example

by Douglas Perry

CHAPTER 14

CPU: RTL Simulation

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