VLSI Design Methodology Development, First Edition

Chapter 3. Hierarchical Design Decomposition

3.1 Logical-to-Physical Correspondence

As illustrated in Figure 3.1, two hierarchical models are maintained for an SoC design: a logical hierarchy and a physical hierarchy. The functional validation environment is developed around the logical hierarchy, with references to model registers and array storage that reflect the instance path concatenation. In addition to the top node of each model representing the full-chip SoC, there are correspondence points throughout the two hierarchies. Below the correspondence nodes in each model, the hierarchical decomposition diverges.

Figure 3.1 Illustration of ...