VLSI Design Methodology Development, First Edition

Chapter 7. Logic Synthesis

7.1 Level of Hardware Description Language Modeling

This section briefly reviews the topics introduced in Section 4.1. There are three principal semantic styles for HDL coding: behavioral, register-transfer level (RTL), and structural cell-level netlist.

Behavioral-level models utilize the concurrent sequential process (CSP) paradigm for time-based model simulation. Behavioral models allow a sequential statement flow within an active process evaluation that assigns a new signal value on a subset of the possible execution paths; as a result, there is an inferred signal state that retains its value when not explicitly assigned. The RTL coding style explicitly defines all data registers and finite state machine elements, ...