VLSI Digital Signal Processing Systems: Design and Implementation

10.2    PIPELINE INTERLEAVING IN DIGITAL FILTERS

In this section, we review the notion of pipeline interleaving in the context of a simple 1st-order recursive digital filter. Three forms of pipeline interleaving are discussed:

1.  Inefficient single/multichannel interleaving.

2.  Efficient single-channel interleaving.

3.  Efficient multichannel interleaving.

In 1, the loop is pipelined without changing the structure of the algorithm and thus hardware is not fully utilized, since zero-samples need to be interleaved to preserve the integrity of the algorithm. In 2 and 3, the interned structure of the algorithm is changed in a way that the pipeline is maximally or fully utilized.

10.2.1    Inefficient Single/Multichannel Interleaving

Consider a 1st-order linear time-invariant recursion described by

and shown in Fig. 10.1(a) in the form of a computation graph. The iteration period of this computation graph is (T_m + T_a), where T_m and T_a, respectively, represent the word-level multiplication time and addition time.

Consider an M-stage pipelined version of this implementation obtained by inserting (M − 1) additional latches inside the loop as shown in Fig. 10.1(b) (at the appropriate places). Then the clock period of this implementation can, in principle, be reduced by M times, but the latency associated with the loop computation and the sample period of the implementation will increase ...