VLSI Digital Signal Processing Systems: Design and Implementation

16.1    INTRODUCTION

The need for high performance and low cost digital systems for signal/image processing applications has resulted in a major thrust for high-speed VLSI design. Traditionally, high throughput is obtained by dividing the combinatorial logic into a number of stages separated by registers/latches controlled by a global clock. Various clocking styles can be used depending on the type of application; these include 2-phase, true single phase, etc. With the advent of technology, the number of transistors that can be integrated on a single chip has increased tremendously. Along with it the clock frequencies at which these chips can operate is also increasing at a rapid rate. Consequently, clock distribution and minimization of clock skew have become major bottlenecks in the design of synchronous systems. In fact, the clock skew may build up to dangerous proportions and cause malfunctioning of the circuit. Therefore, alternative techniques are being explored and most prominent among them are wave pipelining [1] – [6] and asynchronous pipelining [7] – [18].

Wave pipelining is a technique employed to decrease the effective number of pipeline stages in a digital system without increasing the number of physical registers in the pipeline. This is achieved by applying new data to the inputs of the combinational logic before the output (due to previous data inputs) is available, thus pipelining the combinational logic. The time of application of new data is determined by performing ...