The choice of an appropriate logic style is crucial in any wave-pipelined implementation because mismatches in propagation delays at the level of the basic building blocks may cause the architecture to fail. The use of CMOS technology is desirable as it offers increased packing density and reduced power dissipation. However, static CMOS is not an ideal choice for wave pipelining because its propagation delay is highly data dependent. For example, the rise/fall times of a 2-input NAND gate may vary as much as 50%, depending on whether both the input signals are 0 or only 1 of them is 0. Therefore, many logic styles have been proposed to design wave-pipelined architectures. This section addresses only one such style known as the NPCPL [2].

16.6.1    NPCPL

The normal process complementary pass transistor logic (NPCPL) attempts to exploit the advantages of NMOS-only pass transistor logic in a process that requires no threshold adjustment of the pass elements. It consists of

  • true and complementary inputs
  • two pass blocks generating true and complementary output variables
  • level restoring inverters to restore the degraded voltage levels at the output of the pass block to full CMOS levels.

The logic threshold of the inverter used in the logic can be set in accordance with the equation


where The value thus obtained is taken as a starting ...

Get VLSI Digital Signal Processing Systems: Design and Implementation now with O’Reilly online learning.

O’Reilly members experience live online training, plus books, videos, and digital content from 200+ publishers.