VLSI Digital Signal Processing Systems: Design and Implementation

16.7    ASYNCHRONOUS PIPELINING

Most of the present-day systems are clock based or synchronous. These systems are built from subsystems, where each subsystem is a finite-state machine. The subsystems change from one state to another depending on a global clock signal, with flip-flops (registers) being used to store the different states. The state updates within the flip-flops are carried out on the rising (falling) edge of the clock signal. A typical synchronous system is shown in Fig. 16.30(a). Although this approach has made great strides in the design of digital systems, it is beginning to hit some fundamental limitations. A clock-based system can operate correctly only if all parts of the system see the clock at the same time, which can happen only if the delay on the clock wire is negligible. However, with advancement in technology, the systems tend to get bigger and bigger, and as a result the delay on the clock wires can no longer be ignored. The problem of clock skew is thus becoming a bottleneck for many system designers.

The second problem facing system designers is that of power. Logically speaking, this should correspond to the various gates in a system doing some useful work. However, in synchronous systems, this is not the case. Many gates switch unnecessarily just because they are connected to the clock, and not because they have to process new inputs. In fact, the biggest gate is the clock driver itself which must switch even if a small part of the system has something ...