Beautiful Architecture

The Interprocessor Bus

All communication between CPUs goes via the interprocessor bus, or IPB. There are in fact two buses, called X and Y (see Figure 8-1), in case one fails. Unlike other components, both buses are used in parallel when they’re up.

Data is passed across the bus in fixed-length packets of 16 words. The bus is fast enough to saturate memory on both CPUs, so the client CPU performs it synchronously in the dispatcher (scheduler) using the SEND instruction. The destination (server) CPU reserves buffer space for a single transfer at boot time. On completion of the transfer, the destination CPU receives a bus receive interrupt and handles the packet.