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ADVANCED CPU DESIGN
The previous chapter presented a minimal CPU design in digital logic. In this chapter, we’ll look at extending that basic design to increase performance. These extensions include using more registers, using stack architectures that improve subroutine capabilities and speed, adding interrupt requests to enable I/O and operating systems, floating-point hardware, and pipelining and out-of-order execution to enable “superscalar” execution of more than one instruction per clock cycle. At this level of complexity we won’t give full details on how to implement the extensions yourself with digital logic, but you’re welcome to try! ...
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