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Computer Organization and Design RISC-V Edition

Name: Computer Organization and Design RISC-V Edition
ISBN: 9780128122761

by David A. Patterson, John L. Hennessy

May 2017

Intermediate to advanced

696 pages

33h 52m

English

Morgan Kaufmann

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Cover image
Title page
Table of Contents
In Praise of Computer Organization and Design: The Hardware/Software Interface
Copyright
Dedication
Acknowledgments
Preface
About This BookAbout the Other BookWhy RISC-V for This Edition?Changes for the Fifth EditionInstructor SupportConcluding RemarksAcknowledgments
1. Computer Abstractions and Technology
Abstract1.1 Introduction1.2 Eight Great Ideas in Computer Architecture1.3 Below Your Program1.4 Under the Covers1.5 Technologies for Building Processors and Memory1.6 Performance1.7 The Power Wall1.8 The Sea Change: The Switch from Uniprocessors to Multiprocessors1.9 Real Stuff: Benchmarking the Intel Core i71.10 Fallacies and Pitfalls1.11 Concluding RemarksHistorical Perspective and Further Reading1.12 Historical Perspective and Further Reading1.13 Exercises
2. Instructions: Language of the Computer
Abstract2.1 Introduction2.2 Operations of the Computer Hardware2.3 Operands of the Computer Hardware2.4 Signed and Unsigned Numbers2.5 Representing Instructions in the Computer2.6 Logical Operations2.7 Instructions for Making Decisions2.8 Supporting Procedures in Computer Hardware

2.9 Communicating with People
2.10 RISC-V Addressing for Wide Immediates and Addresses2.11 Parallelism and Instructions: Synchronization2.12 Translating and Starting a Program2.13 A C Sort Example to Put it All Together
2.14 Arrays versus Pointers
Advanced Material: Compiling C and Interpreting Java2.15 Advanced Material: Compiling C and Interpreting Java2.16 Real Stuff: MIPS Instructions2.17 Real Stuff: x86 Instructions2.18 Real Stuff: The Rest of the RISC-V Instruction Set2.19 Fallacies and Pitfalls2.20 Concluding RemarksHistorical Perspective and Further Reading2.22 Historical Perspective and Further Reading2.22 Exercises
3. Arithmetic for Computers
Abstract3.1 Introduction3.2 Addition and Subtraction3.3 Multiplication3.4 Division3.5 Floating Point3.6 Parallelism and Computer Arithmetic: Subword Parallelism3.7 Real Stuff: Streaming SIMD Extensions and Advanced Vector Extensions in x863.8 Going Faster: Subword Parallelism and Matrix Multiply3.9 Fallacies and Pitfalls3.10 Concluding RemarksHistorical Perspective and Further ReadingHistorical Perspective and Further Reading3.12 Exercises
4. The Processor
Abstract4.1 Introduction4.2 Logic Design Conventions4.3 Building a Datapath4.4 A Simple Implementation Scheme4.5 An Overview of Pipelining4.6 Pipelined Datapath and Control4.7 Data Hazards: Forwarding versus Stalling4.8 Control Hazards
4.9 Exceptions
4.10 Parallelism via Instructions4.11 Real Stuff: The ARM Cortex-A53 and Intel Core i7 Pipelines4.12 Going Faster: Instruction-Level Parallelism and Matrix MultiplyAdvanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations4.13 Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations4.14 Fallacies and Pitfalls4.15 Concluding RemarksHistorical Perspective and Further Reading4.16 Historical Perspective and Further Reading4.17 Exercises
5. Large and Fast: Exploiting Memory Hierarchy
Abstract5.1 Introduction5.2 Memory Technologies5.3 The Basics of Caches5.4 Measuring and Improving Cache Performance5.5 Dependable Memory Hierarchy5.6 Virtual Machines5.7 Virtual Memory
5.8 A Common Framework for Memory Hierarchy
5.9 Using a Finite-State Machine to Control a Simple Cache5.10 Parallelism and Memory Hierarchy: Cache CoherenceParallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks5.11 Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive DisksAdvanced Material: Implementing Cache Controllers5.12 Advanced Material: Implementing Cache Controllers5.13 Real Stuff: The ARM Cortex-A53 and Intel Core i7 Memory Hierarchies5.14 Real Stuff: The Rest of the RISC-V System and Special Instructions5.15 Going Faster: Cache Blocking and Matrix Multiply5.16 Fallacies and Pitfalls5.17 Concluding RemarksHistorical Perspective and Further Reading5.18 Historical Perspective and Further Reading5.19 Exercises
6. Parallel Processors from Client to Cloud
Abstract6.1 Introduction6.2 The Difficulty of Creating Parallel Processing Programs6.3 SISD, MIMD, SIMD, SPMD, and Vector6.4 Hardware Multithreading6.5 Multicore and Other Shared Memory Multiprocessors6.6 Introduction to Graphics Processing Units6.7 Clusters, Warehouse Scale Computers, and Other Message-Passing Multiprocessors
6.8 Introduction to Multiprocessor Network Topologies
Communicating to the Outside World: Cluster Networking6.9 Communicating to the Outside World: Cluster Networking6.10 Multiprocessor Benchmarks and Performance Models6.11 Real Stuff: Benchmarking and Rooflines of the Intel Core i7 960 and the NVIDIA Tesla GPU6.12 Going Faster: Multiple Processors and Matrix Multiply6.13 Fallacies and Pitfalls6.14 Concluding RemarksHistorical Perspective and Further Reading6.15 Historical Perspective and Further Reading6.16 Exercises
Appendix
Appendix A. The Basics of Logic Design
A.1 IntroductionA.2 Gates, Truth Tables, and Logic EquationsA.3 Combinational LogicA.4 Using a Hardware Description LanguageA.5 Constructing a Basic Arithmetic Logic Unit
A.6 Faster Addition: Carry Lookahead
A.7 ClocksA.8 Memory Elements: Flip-Flops, Latches, and RegistersA.9 Memory Elements: SRAMs and DRAMsA.10 Finite-State MachinesA.11 Timing MethodologiesA.12 Field Programmable DevicesA.13 Concluding RemarksA.14 Exercises
Appendix B. Graphics and Computing GPUs
B.1 IntroductionB.2 GPU System ArchitecturesB.3 Programming GPUsB.4 Multithreaded Multiprocessor ArchitectureB.5 Parallel Memory SystemB.6 Floating-point ArithmeticB.7 Real Stuff: The NVIDIA GeForce 8800B.8 Real Stuff: Mapping Applications to GPUsB.9 Fallacies and PitfallsB.10 Concluding RemarksB.11 Historical Perspective and Further ReadingFurther Reading
Appendix C. Mapping Control to Hardware
C.1 IntroductionC.2 Implementing Combinational Control UnitsC.3 Implementing Finite-State Machine ControlC.4 Implementing the Next-State Function with a SequencerC.5 Translating a Microprogram to HardwareC.6 Concluding RemarksC.7 Exercises
Appendix D. A Survey of RISC Architectures for Desktop, Server, and Embedded Computers
D.1 IntroductionD.2 Addressing Modes and Instruction FormatsD.3 Instructions: The MIPS Core SubsetD.4 Instructions: Multimedia Extensions of the Desktop/Server RISCsD.5 Instructions: Digital Signal-Processing Extensions of the Embedded RISCsD.6 Instructions: Common Extensions to MIPS CoreD.7 Instructions Unique to MIPS-64D.8 Instructions Unique to AlphaD.9 Instructions Unique to SPARC v9D.10 Instructions Unique to PowerPCD.11 Instructions Unique to PA-RISC 2.0D.12 Instructions Unique to ARMD.13 Instructions Unique to ThumbD.14 Instructions Unique to SuperHD.15 Instructions Unique to M32RD.16 Instructions Unique to MIPS-16D.17 Concluding RemarksFurther Reading
Answers to Check Yourself
Chapter 1Chapter 2Chapter 3Chapter 4Chapter 5Chapter 6
Glossary
Further Reading
Index
RISC-V Reference Data Card (“Green Card”)

Content preview from Computer Organization and Design RISC-V Edition

text segment

The segment of a UNIX object file that contains the machine language code for routines in the source file.

Figure 2.13 **The RISC-V memory allocation for program and data.**These addresses are only a software convention, and not part of the RISC-V architecture. The user address space is set to 2³⁸ of the potential 2⁶⁴ total address space given a 64-bit architecture (see Chapter 5). The stack pointer is initialized to 0000 003f ffff fff0_hex and grows down toward the data segment. At the other end, the program code (“text”) starts at 0000 0000 0040 0000_hex. The static data starts immediately after the end of the text segment; in this ...

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Computer Organization and Design RISC-V Edition

by David A. Patterson, John L. Hennessy

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