Computer Organization and Design RISC-V Edition

Lookup tables (LUTs), A-77–A-78

Loop unrolling

defined, 327–328, 144.e3–144.e4

for multiple-issue pipelines, 327b–328b

register renaming and, 327

Loops, 94–96

conditional branches in, 115–116

for, 142

prediction and, 312b

test, 142, 143

while, compiling, 94b–95b

lr.d (load reserved), 64f

lui (load upper immediate), 64f

lw (load word), 64f

lwu (load word, unsigned), 64f

M

M32R, D-15, D-40

Machine code, 82

Machine instructions, 82

Machine language, 15f

branch offset in, 116b–117b

decoding, 118–120

defined, 14, 82

illustrated, 15f

RISC-V, 87–89

SRAM, 19–22

translating RISC-V assembly language into, 85b–86b

Main memory, 420See also Memory

defined, 23

page tables, 429

physical addresses, 420

Mapping ...