Dependable Computing

4Processor Level Error Detection and Recovery

4.1 Introduction

Traditionally, transient faults have been linked to the corruption of stored data values. As early as 1954, the phenomenon has been reported in adverse operating conditions, e.g., near nuclear bomb test sites and in space applications [1, 2]. Beginning in 1978, dense memory circuits (both DRAM and SRAM) have been known to be at risk to soft errors caused by alpha particles from IC (integrated circuit) packaging [3] and cosmic rays [4]. A hardware device can generally recover its full capability after a transient failure. Nonetheless, such failures can be catastrophic for the proper execution of a program, as a corrupted intermediate value, if not dealt with, can corrupt subsequent computations. Through the years, means to guard against soft errors in memory devices have evolved to include physical techniques in cell and gate design [5] and in packaging materials [6], in addition to error correction codes (ECC). These techniques are now routinely used, even in commodity PC memories. Even so, except in extremely critical applications, protection against transient failures has been given very little commercial attention other than for the memory subsystem. While soft‐error rates vary significantly depending on device types and operating conditions, current estimates typically are in the range of one failure per one million hours [7].

Continuously decreasing feature sizes and supply voltage of devices reduce capacitive ...