Digital Interface Design and Application

Appendix CDAC and ADC Support Software

A summary of the software support provided for digital to analogue converter (DAC) and analogue to digital converter (ADC) subsystems in particular.

C.1 DAC Peripheral Features

DAC channels

• The device integrates two 12-bit DACs that can be used independently or simultaneously (dual mode).

DAC triggers

• DAC conversion can be non-triggered when the related output is available once data is written to the register.

• DAC conversion can be triggered by:
  1. An external event using a related input pin.
  2. A timer generated event.
  3. Using a software command.

DAC buffer mode feature

• Each DAC channel integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without having to add an external operational amplifier. The device data sheet gives more details about the impedance value that can be achieved.

DAC wave generation feature

• Both DAC channels can be used to generate:
  1. A pseudo-random Noise waveform,
  2. A Triangle waveform.

DAC data format

• The DAC data format can be:
  1. 8-bit right alignment,
  2. 12-bit left alignment,
  3. 12-bit right alignment.

DAC data value to voltage correspondence

• The analogue output voltage on each DAC channel pin is determined by the following equation:
  • where DOR is the DAC Data Register and VEF+ is the input reference voltage, typically 3.3 V on the Discovery board. The ...