Book description
New, updated and expanded topics in the fourth edition include: EBCDIC, Grey code, practical applications of flip-flops, linear and shaft encoders, memory elements and FPGAs. The section on fault-finding has been expanded. A new chapter is dedicated to the interface between digital components and analog voltages.- A highly accessible, comprehensive and fully up to date digital systems text
- A well known and respected text now revamped for current courses
- Part of the Newnes suite of texts for HND/1st year modules
Table of contents
- Cover image
- Title page
- Table of Contents
- Dedication
- Copyright
- Preface to the fourth edition
- Acknowledgments
-
Chapter 1: Number systems and codes
- 1.1 Introduction
- 1.2 Number systems
- 1.3 Conversion between number systems
- 1.4 Binary addition and subtraction
- 1.5 Signed arithmetic
- 1.6 Complement arithmetic
- 1.7 Complement representation for binary numbers
- 1.8 The validity of 1’s and 2’s complement arithmetic
- 1.9 Offset binary representation
- 1.10 Addition and subtraction of 2’s complement numbers
- 1.11 Graphical interpretation of 2’s complement representation
- 1.12 Addition and subtraction of 1’s complement numbers
- 1.13 Multiplication of unsigned binary numbers
- 1.14 Multiplication of signed binary numbers
- 1.15 Binary division
- 1.16 Floating point arithmetic
- 1.17 Binary codes for decimal digits
- 1.18 n-cubes and distance
- 1.19 Error detection and correction
- 1.20 The Hamming code
- 1.21 Gray code
- 1.22 The ASCII code
- Problems
-
Chapter 2: Boolean algebra
- 2.1 Introduction
- 2.2 Boolean algebra
- 2.3 Derived Boolean operations
- 2.4 Boolean functions
- 2.5 Truth tables
- 2.6 The logic of a switch
- 2.7 The switch implementation of the AND function
- 2.8 The switch implementation of the OR function
- 2.9 The gating function of the AND and OR gates
- 2.10 The inversion function
- 2.11 Gate or switch implementation of a Boolean function
- 2.12 The Boolean theorems
- 2.13 Complete sets
- 2.14 The exclusive-OR (XOR) function
- 2.15 The Reed–Muller equation
- 2.16 Set theory and the Venn diagram
-
Chapter 3: Karnaugh maps and function simplification
- 3.2 Introduction
- 3.2 Minterms and maxterms
- 3.3 Canonical forms
- 3.4 Boolean functions of two variables
- 3.5 The Karnaugh map
- 3.6 Plotting Boolean functions on a Karnaugh map
- 3.7 Maxterms on the Karnaugh map
- 3.8 Simplification of Boolean functions
- 3.9 The inverse function
- 3.10 ‘Don’t care’ terms
- 3.11 Simplification of products of maxterms
- 3.12 The Quine–McCluskey tabular simplification method
- 3.13 Properties of prime implicant tables
- 3.14 Cyclic prime implicant tables
- 3.15 Semi-cyclic prime implicant tables
- 3.16 Quine–McCluskey simplification of functions containing ‘don’t care’ terms
- 3.17 Decimal approach to Quine–McCluskey simplification of Boolean functions
- 3.18 Multiple output circuits
- 3.19 Tabular methods for multiple output functions
- 3.20 Reduced dimension maps
- 3.21 Plotting RDMs from truth tables
- 3.22 Reading RDM functions
- 3.23 Looping rules for RDMs
- 3.24 Criteria for minimisation
- Problems
-
Chapter 4: Combinational logic design principles
- 4.1 Introduction
- 4.2 The NAND function
- 4.3 NAND logic implementation of AND and OR functions
- 4.4 NAND logic implementation of sums-of-products
- 4.5 The NOR function
- 4.6 NOR logic implementation of AND and OR functions
- 4.7 NOR logic implementation of products-of-sums
- 4.8 NOR logic implementation of sums-of-products
- 4.9 Boolean algebraic analysis of NAND and NOR networks
- 4.10 Symbolic circuit analysis for NAND and NOR networks
- 4.11 Alternative function representations
- 4.12 Gate signal conventions
- 4.13 Gate expansion
- 4.14 Miscellaneous gate networks
- 4.15 Exclusive-OR and exclusive-NOR
- 4.16 Noise margins
- 4.17 Propagation time
- 4.18 Speed-power products
- 4.19 Fan-out
- Problems
-
Chapter 5: Combinational logic design with MSI circuits
- 5.1 Introduction
- 5.2 Multiplexers and data selection
- 5.3 Available MSI multiplexers
- 5.4 Interconnecting multiplexers
- 5.5 The multiplexer as a Boolean function generator
- 5.6 Multi-level multiplexing
- 5.7 Demultiplexers
- 5.8 Multiplexer/demultiplexer data transmission system
- 5.9 Decoders
- 5.10 Decoder networks
- 5.11 The decoder as a minterm generator
- 5.12 Display decoding
- 5.13 Encoder circuit principles
- 5.14 Available MSI encoders
- 5.15 Encoding networks
- 5.16 Parity generation and checking
- 5.17 Digital comparators
- 5.18 Iterative circuits
-
Chapter 6: Latches and flip-flops
- 6.1 Introduction
- 6.2 The bistable element
- 6.3 The SR latch
- 6.4 The controlled SR latch
- 6.5 The controlled D latch
- 6.6 Latch timing parameters
- 6.7 The JK flip-flop
- 6.8 The master/slave JK flip-flop
- 6.9 Asynchronous controls (direct preset and clear)
- 6.10 1’s and 0’s catching
- 6.11 The master/slave SR flip-flop
- 6.12 The edge-triggered D flip-flop
- 6.13 The edge-triggered JK flip-flop
- 6.14 The T flip-flop
- 6.15 Mechanical switch debouncing
- 6.16 Registers
- Problems
-
Chapter 7: Counters and registers
- 7.1 Introduction
- 7.2 The clock signal
- 7.3 Basic counter design
- 7.4 Series and parallel connection of counters
- 7.5 Scale-of-five up-counter
- 7.6 The design steps for a synchronous counter
- 7.7 Gray code counters
- 7.8 Design of decade Gray code up-counter
- 7.9 Scale-of-16 up/down counter
- 7.10 Asynchronous binary counters
- 7.11 Decoding of asynchronous counters
- 7.12 Asynchronous resettable counters
- 7.13 Integrated circuit counters
- 7.14 Cascading of IC counter chips
- 7.15 Shift registers
- 7.16 The 4-bit 7494 shift register
- 7.17 The 4-bit 7495 universal shift register
- 7.18 The 74165 parallel loading 8-bit shift register
- 7.19 The use of shift registers as counters and sequence generators
- 7.20 The universal state diagram for shift registers
- 7.21 The design of a decade counter
- 7.22 The ring counter
- 7.23 The twisted ring or Johnson counter
- 7.24 Series and parallel interconnection of Johnson counters
- 7.25 Shift registers with XOR feedback
- 7.26 Multi-bit rate multipliers
- Problems
-
Chapter 8: Clock-driven sequential circuits
- 8.1 Introduction
- 8.2 The basic synchronous sequential circuit
- 8.3 Analysis of a clocked sequential circuit
- 8.4 Design steps for synchronous sequential circuits
- 8.5 The design of a sequence detector
- 8.6 The Moore and Mealy state machines
- 8.7 Analysis of a sequential circuit implemented with JK flip-flops
- 8.8 Sequential circuit design using JK flip-flops
- 8.9 State reduction
- 8.10 State assignment
- 8.11 Algorithmic state machine charts
- 8.12 Conversion of an ASM chart into hardware
- 8.13 The ‘one-hot’ state assignment
- 8.14 Clock skew
- 8.15 Clock timing constraints
- 8.16 Asynchronous inputs
- 8.17 The handshake
- Problems
-
Chapter 9: Event driven circuits
- 9.1 Introduction
- 9.2 Design procedure for asynchronous sequential circuits
- 9.3 Stable and unstable states
- 9.4 Design of a lamp switching circuit
- 9.5 Races
- 9.6 Race free assignments
- 9.7 The pump problem
- 9.8 Design of a sequence detector
- 9.9 State reduction for incompletely specified machines
- 9.10 Compatibility
- 9.11 Determination of compatible pairs
- 9.12 The merger diagram
- 9.13 The state reduction procedure
- 9.14 Circuit hazards
- 9.15 Gate delays
- 9.16 The generation of spikes
- 9.17 The generation of static hazards in combinational networks
- 9.18 The elimination of static hazards
- 9.19 Design of hazard-free combinational networks
- 9.20 Detection of hazards in an existing network
- 9.21 Hazard-free asynchronous circuit design
- 9.22 Dynamic hazards
- 9.23 Function hazards
- 9.24 Essential hazards
-
Chapter 10: Instrumentation and interfacing
- 10.1 Introduction
- 10.2 Schmitt trigger circuits
- 10.3 Schmitt input gates
- 10.4 Digital-to-analogue conversion
- 10.5 Analogue-to-digital conversion
- 10.6 Flash converters
- 10.7 Integrating A/D converter types
- 10.8 A/D converter types using an embedded D/A converter
- 10.9 Shaft encoders and linear encoders
- 10.10 Sensing of motion
- 10.11 Absolute encoders
- 10.12 Conversion from Gray code to base 2
- 10.13 Petherick code
- 10.14 Incremental encoders
- 10.15 Open collector and tri-state gates
- 10.16 Use of open collector gates
- 10.17 Use of tri-state buffers and gates
- 10.18 Other interfacing components
- Problems
-
Chapter 11: Programmable logic devices
- 11.1 Introduction
- 11.2 Read only memory
- 11.3 ROM timing
- 11.4 Internal ROM structure
- 11.5 Implementation of Boolean functions using ROMs
- 11.7 Memory addressing
- 11.8 Design of sequential circuits using ROMs
- 11.9 Programmable logic devices (PLDs)
- 11.10 Programmable gate arrays (PGAs)
- 11.11 Programmable logic arrays (PLAs)
- 11.12 Programmable array logic (PAL)
- 11.13 Programmable logic sequencers (PLSs)
- 11.14 Field programmable gate arrays (FPGAs)
- 11.15 Xilinx field programmable gate arrays
- 11.16 Actel programmable gate arrays
- 11.17 Altera erasable programmable logic devices
- Problems
-
Chapter 12: Arithmetic circuits
- 12.1 Introduction
- 12.2 The half adder
- 12.3 The full adder
- 12.4 Binary subtraction
- 12.5 The 4-bit binary full adder
- 12.6 Carry look-ahead addition
- 12.7 The 74283 4-bit carry look-ahead adder
- 12.8 Addition/subtraction circuits using complement arithmetic
- 12.9 Overflow
- 12.10 Serial addition and subtraction
- 12.11 Accumulating adder
- 12.12 Decimal arithmetic with MSI adders
- 12.13 Adder/subtractor for decimal arithmetic
- 12.14 The 7487 true/complement unit
- 12.15 Arithmetic/logic unit design
- 12.16 Available MSI arithmetic/logic units
- 12.17 Multiplication
- 12.18 Combinational multipliers
- 12.19 ROM implemented multiplier
- 12.20 The shift and add multiplier
- 12.21 Available multiplier packages
- 12.22 Signed arithmetic
- 12.23 Booth’s algorithm
- 12.24 Implementation of Booth’s algorithm
-
Chapter 13: Fault diagnosis and testing
- 13.1 Introduction
- 13.2 Fault detection and location
- 13.3 Gate sensitivity
- 13.4 A fault test for a 2-input AND gate
- 13.5 Path sensitisation
- 13.6 Path sensitisation in networks with fan-out
- 13.7 Undetectable faults
- 13.8 Bridging faults
- 13.9 The fault detection table
- 13.10 Two-level circuit fault detection in AND/OR circuits
- 13.11 Two-level circuit fault detection in OR/AND circuits
- 13.12 Boolean difference
- 13.13 Compact testing techniques
- 13.14 Signature analysis
- 13.15 The scan path testing technique
- 13.16 Designing for testability
- I. Problems
- Appendix Functional logic symbols
- Answers to problems
- Bibliography
- Index
Product information
- Title: Digital Logic Design, 4th Edition
- Author(s):
- Release date: November 2002
- Publisher(s): Newnes
- ISBN: 9780080477305
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