book

Digital Logic Design, 4th Edition

by Brian Holdsworth, Clive Woods

November 2002

Intermediate to advanced

519 pages

16h 45m

English

Newnes

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Cover image
Title page
Table of Contents
Dedication
Copyright
Preface to the fourth edition
Acknowledgments
Chapter 1: Number systems and codes
1.1 Introduction1.2 Number systems1.3 Conversion between number systems1.4 Binary addition and subtraction1.5 Signed arithmetic1.6 Complement arithmetic1.7 Complement representation for binary numbers1.8 The validity of 1’s and 2’s complement arithmetic1.9 Offset binary representation1.10 Addition and subtraction of 2’s complement numbers1.11 Graphical interpretation of 2’s complement representation1.12 Addition and subtraction of 1’s complement numbers1.13 Multiplication of unsigned binary numbers1.14 Multiplication of signed binary numbers1.15 Binary division1.16 Floating point arithmetic1.17 Binary codes for decimal digits1.18 n-cubes and distance1.19 Error detection and correction1.20 The Hamming code1.21 Gray code1.22 The ASCII codeProblems
Chapter 2: Boolean algebra
2.1 Introduction2.2 Boolean algebra2.3 Derived Boolean operations2.4 Boolean functions2.5 Truth tables2.6 The logic of a switch2.7 The switch implementation of the AND function2.8 The switch implementation of the OR function2.9 The gating function of the AND and OR gates2.10 The inversion function2.11 Gate or switch implementation of a Boolean function2.12 The Boolean theorems2.13 Complete sets2.14 The exclusive-OR (XOR) function2.15 The Reed–Muller equation2.16 Set theory and the Venn diagram
Chapter 3: Karnaugh maps and function simplification
3.2 Introduction3.2 Minterms and maxterms3.3 Canonical forms3.4 Boolean functions of two variables3.5 The Karnaugh map3.6 Plotting Boolean functions on a Karnaugh map3.7 Maxterms on the Karnaugh map3.8 Simplification of Boolean functions3.9 The inverse function3.10 ‘Don’t care’ terms3.11 Simplification of products of maxterms3.12 The Quine–McCluskey tabular simplification method3.13 Properties of prime implicant tables3.14 Cyclic prime implicant tables3.15 Semi-cyclic prime implicant tables3.16 Quine–McCluskey simplification of functions containing ‘don’t care’ terms3.17 Decimal approach to Quine–McCluskey simplification of Boolean functions3.18 Multiple output circuits3.19 Tabular methods for multiple output functions3.20 Reduced dimension maps3.21 Plotting RDMs from truth tables3.22 Reading RDM functions3.23 Looping rules for RDMs3.24 Criteria for minimisationProblems

Chapter 4: Combinational logic design principles
4.1 Introduction4.2 The NAND function4.3 NAND logic implementation of AND and OR functions4.4 NAND logic implementation of sums-of-products4.5 The NOR function4.6 NOR logic implementation of AND and OR functions4.7 NOR logic implementation of products-of-sums4.8 NOR logic implementation of sums-of-products4.9 Boolean algebraic analysis of NAND and NOR networks4.10 Symbolic circuit analysis for NAND and NOR networks4.11 Alternative function representations4.12 Gate signal conventions4.13 Gate expansion4.14 Miscellaneous gate networks4.15 Exclusive-OR and exclusive-NOR4.16 Noise margins4.17 Propagation time4.18 Speed-power products4.19 Fan-outProblems
Chapter 5: Combinational logic design with MSI circuits
5.1 Introduction5.2 Multiplexers and data selection5.3 Available MSI multiplexers5.4 Interconnecting multiplexers5.5 The multiplexer as a Boolean function generator5.6 Multi-level multiplexing5.7 Demultiplexers5.8 Multiplexer/demultiplexer data transmission system5.9 Decoders5.10 Decoder networks5.11 The decoder as a minterm generator5.12 Display decoding5.13 Encoder circuit principles5.14 Available MSI encoders5.15 Encoding networks5.16 Parity generation and checking5.17 Digital comparators5.18 Iterative circuits
Chapter 6: Latches and flip-flops
6.1 Introduction6.2 The bistable element6.3 The SR latch6.4 The controlled SR latch6.5 The controlled D latch6.6 Latch timing parameters6.7 The JK flip-flop6.8 The master/slave JK flip-flop6.9 Asynchronous controls (direct preset and clear)6.10 1’s and 0’s catching6.11 The master/slave SR flip-flop6.12 The edge-triggered D flip-flop6.13 The edge-triggered JK flip-flop6.14 The T flip-flop6.15 Mechanical switch debouncing6.16 RegistersProblems
Chapter 7: Counters and registers
7.1 Introduction7.2 The clock signal7.3 Basic counter design7.4 Series and parallel connection of counters7.5 Scale-of-five up-counter7.6 The design steps for a synchronous counter7.7 Gray code counters7.8 Design of decade Gray code up-counter7.9 Scale-of-16 up/down counter7.10 Asynchronous binary counters7.11 Decoding of asynchronous counters7.12 Asynchronous resettable counters7.13 Integrated circuit counters7.14 Cascading of IC counter chips7.15 Shift registers7.16 The 4-bit 7494 shift register7.17 The 4-bit 7495 universal shift register7.18 The 74165 parallel loading 8-bit shift register7.19 The use of shift registers as counters and sequence generators7.20 The universal state diagram for shift registers7.21 The design of a decade counter7.22 The ring counter7.23 The twisted ring or Johnson counter7.24 Series and parallel interconnection of Johnson counters7.25 Shift registers with XOR feedback7.26 Multi-bit rate multipliersProblems
Chapter 8: Clock-driven sequential circuits
8.1 Introduction8.2 The basic synchronous sequential circuit8.3 Analysis of a clocked sequential circuit8.4 Design steps for synchronous sequential circuits8.5 The design of a sequence detector8.6 The Moore and Mealy state machines8.7 Analysis of a sequential circuit implemented with JK flip-flops8.8 Sequential circuit design using JK flip-flops8.9 State reduction8.10 State assignment8.11 Algorithmic state machine charts8.12 Conversion of an ASM chart into hardware8.13 The ‘one-hot’ state assignment8.14 Clock skew8.15 Clock timing constraints8.16 Asynchronous inputs8.17 The handshakeProblems
Chapter 9: Event driven circuits
9.1 Introduction9.2 Design procedure for asynchronous sequential circuits9.3 Stable and unstable states9.4 Design of a lamp switching circuit9.5 Races9.6 Race free assignments9.7 The pump problem9.8 Design of a sequence detector9.9 State reduction for incompletely specified machines9.10 Compatibility9.11 Determination of compatible pairs9.12 The merger diagram9.13 The state reduction procedure9.14 Circuit hazards9.15 Gate delays9.16 The generation of spikes9.17 The generation of static hazards in combinational networks9.18 The elimination of static hazards9.19 Design of hazard-free combinational networks9.20 Detection of hazards in an existing network9.21 Hazard-free asynchronous circuit design9.22 Dynamic hazards9.23 Function hazards9.24 Essential hazards
Chapter 10: Instrumentation and interfacing
10.1 Introduction10.2 Schmitt trigger circuits10.3 Schmitt input gates10.4 Digital-to-analogue conversion10.5 Analogue-to-digital conversion10.6 Flash converters10.7 Integrating A/D converter types10.8 A/D converter types using an embedded D/A converter10.9 Shaft encoders and linear encoders10.10 Sensing of motion10.11 Absolute encoders10.12 Conversion from Gray code to base 210.13 Petherick code10.14 Incremental encoders10.15 Open collector and tri-state gates10.16 Use of open collector gates10.17 Use of tri-state buffers and gates10.18 Other interfacing componentsProblems
Chapter 11: Programmable logic devices
11.1 Introduction11.2 Read only memory11.3 ROM timing11.4 Internal ROM structure11.5 Implementation of Boolean functions using ROMs11.7 Memory addressing11.8 Design of sequential circuits using ROMs11.9 Programmable logic devices (PLDs)11.10 Programmable gate arrays (PGAs)11.11 Programmable logic arrays (PLAs)11.12 Programmable array logic (PAL)11.13 Programmable logic sequencers (PLSs)11.14 Field programmable gate arrays (FPGAs)11.15 Xilinx field programmable gate arrays11.16 Actel programmable gate arrays11.17 Altera erasable programmable logic devicesProblems
Chapter 12: Arithmetic circuits
12.1 Introduction12.2 The half adder12.3 The full adder12.4 Binary subtraction12.5 The 4-bit binary full adder12.6 Carry look-ahead addition12.7 The 74283 4-bit carry look-ahead adder12.8 Addition/subtraction circuits using complement arithmetic12.9 Overflow12.10 Serial addition and subtraction12.11 Accumulating adder12.12 Decimal arithmetic with MSI adders12.13 Adder/subtractor for decimal arithmetic12.14 The 7487 true/complement unit12.15 Arithmetic/logic unit design12.16 Available MSI arithmetic/logic units12.17 Multiplication12.18 Combinational multipliers12.19 ROM implemented multiplier12.20 The shift and add multiplier12.21 Available multiplier packages12.22 Signed arithmetic12.23 Booth’s algorithm12.24 Implementation of Booth’s algorithm
Chapter 13: Fault diagnosis and testing
13.1 Introduction13.2 Fault detection and location13.3 Gate sensitivity13.4 A fault test for a 2-input AND gate13.5 Path sensitisation13.6 Path sensitisation in networks with fan-out13.7 Undetectable faults13.8 Bridging faults13.9 The fault detection table13.10 Two-level circuit fault detection in AND/OR circuits13.11 Two-level circuit fault detection in OR/AND circuits13.12 Boolean difference13.13 Compact testing techniques13.14 Signature analysis13.15 The scan path testing technique13.16 Designing for testabilityI. Problems
Appendix Functional logic symbols
Answers to problems
Bibliography
Index

Content preview from Digital Logic Design, 4th Edition

Copyright

Newnes

An imprint of Elsevier Science

Linacre House, Jordan Hill, Oxford OX2 8DP

225 Wildwood Avenue, Woburn, MA 01801-2041

First published 1982

Second edition 1987

Third edition 1993

Fourth edition 2002

The right of Brian Holdsworth and Clive Woods to be identified as the authors of this work has been asserted in accordance with the Copyright, Designs and Patents Act 1988

No part of this publication may be reproduced in any material form (including photocopying or storing in any medium by electronic means and whether or not transiently or incidentally to some other use of this publication) without the written permission of the copyright holder except in accordance ...

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Digital Logic Design, 4th Edition

by Brian Holdsworth, Clive Woods

Copyright

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