Digital Logic Testing and Simulation, 2nd Edition

INDEX

Symbols

@ symbol 292

Numerics

0-1 transition 523

0-controllability 397–398

1-0 transition 523

1-controllability 397, 399, 401

74181 ALU

Verilog model 359–360

gate-level drawing 376

95% confidence level 347

9-value ITG 246–249, 278

A

A-algorithm (AALG) 184–188

back propagation 185–188

chain segment 187–188

DRBACK 187–188

DROPIT 187–188

flexible signal(s) 185–187

Abbreviated descriptor cell 145, 149

ABIST (array BIST) 479

ABT test 477

AC test 298

Acceptable fault coverage 471

Acceptable quality level (AQL) 2, 17, 23, 348, 388, 551

Accumulate signatures 460

Accuracy, definition of 285

Action/check pair 587

Active fault tolerance 495, 499

Activity vector 180–181

Acyclic circuit 40, 92, 260, 263

Adaptive experiments 266

Addition of two vectors 538

Address decoder faults 522

Address lines 515

Addressable Registers 411–412, 415

Ad-hoc DFT solutions 388–389, 393–395

Ad-hoc techniques 635

AHPL (A Hardware Programming Language) 35, 597–598, 601, 604

Algorithmic test 356–361

Aliasing 470–471

Almost-full-scan 427

Alpha particles 537

Ambiguity

simulation 272

state machine 267–269, 272–275

Ambiguous region 63

AmZ8065 Burst Error Processor 502

Analysis of a Faulted Circuit 122–125

AQL see Acceptable quality level

Artificial intelligence (AI) 599

Assertion checker 577

Asynchronous circuit 40, 61

ATLAS (Abbreviated Test Language for All Systems) 320

Atomic proposition(s) 636, 642, 646

ATPG/fault ...