Book description
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book.- Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly
- Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence
- Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products
- Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes
Table of contents
- Brief Table of Contents
- Table of Contents
- The Morgan Kaufmann Series in Systems on Silicon
- Copyright
- Preface
- In the Classroom
- Acknowledgments
- Contributors
- About the Editors
- Chapter 1. Introduction
- Bibliography
- References
- R1.0 Books
- R1.1 Overview of Electronic Design Automation
- R1.2 Logic Design Automation
- R1.3 Test Automation
- R1.4 Physical Design Automation
- R1.5 Concluding Remarks
- Chapter 2. Fundamentals of CMOS design
- Bibliography
- References
- R2.0 Books
- R2.6 Low-Power Design
- Chapter 3. Design for testability
- Bibliography
- References
- R3.0 Books
- R3.1 Introduction
- R3.2 Testability Analysis
- R3.3 Scan Design
- R3.4 Logic Built-in Self-Test
- R3.5 Test Compression
- R3.6 Concluding Remarks
- Chapter 4. Fundamentals of algorithms
- Bibliography
- References
- R4.1 Books
- R4.2 Computational Complexity
- R4.3 Graph Algorithms
- R4.4 Heuristic Algorithms
- R4.5 Mathematical Programming
- Chapter 5. Electronic system-level design and high-level synthesis
- Bibliography
- References
- R5.0 Books
- R5.1 Introduction
- R5.7 Concluding Remarks
- Chapter 6. Logic synthesis in a nutshell
- Bibliography
- References
- R6.0 Books
- R6.1 Introduction
- R6.2 Data Structures for Boolean Representation and Reasoning
- R6.3 Combinational Logic Minimization
- R6.4 Technology Mapping
- R6.5 Timing Analysis
- R6.6 Timing Optimization
- R6.7 Trends in Logic Synthesis
- Chapter 7. Test synthesis
- Bibliography
- References
- R7.0 Books
- R7.1 Introduction
- R7.2 Scan Design
- R7.3 Logic Built-in Self-Test (BIST) Design
- R7.4 RTL Design for Testability
- R7.5 Concluding Remarks
- Chapter 8. Logic and circuit simulation
- Bibliography
- References
- R8.0 Books
- R8.1 Introduction
- R8.2 Logic Simulation Models
- R8.3 Logic Simulation Techniques
- R8.4 Hardware-Accelerated Logic Simulation
- R8.5 Circuit Simulation Models
- R8.7 Simulation of VLSI Interconnects
- R8.8 Simulation of Nonlinear Devices
- R8.9 Concluding Remarks
- Chapter 9. Functional verification
- Bibliography
- References
- R9.0 Books
- R9.1 Introduction
- R9.2 Verification Hierarchy
- R9.3 Measuring Verification Quality
- R9.4 Simulation-Based Approach
- R9.5 Formal Approaches
- R9.6 Advanced Research
- Chapter 10. Floorplanning
- Bibliography
- References
- R10.0 Books
- R10.1 Introduction
- R10.2 Simulated Annealing Approach
- R10.3 Analytical Approach
- R10.4 Modern Floorplanning Considerations
- R10.5 Concluding Remarks
- Chapter 11. Placement
- Bibliography
- References
- R11.0 Books
- R11.1 Introduction
- R11.2 Problem Formulations
- R11.3 Global Placement: Partitioning-Based Approach
- R11.4 Global Placement: Simulated Annealing Approach
- R11.5 Global Placement: Analytical Approach
- R11.6 Legalization
- R11.7 Detailed Placement
- R11.8 Concluding Remarks
- Chapter 12. Global and detailed routing
- Bibliography
- References
- R12.0 Books
- R12.2 Problem Definition
- R12.3 General-Purpose Routing
- R12.4 Global Routing
- R12.5 Detailed Routing
- R12.6 Modern Routing Considerations
- R12.8 Exercises
- Chapter 13. Synthesis of clock and power/ground networks
- Bibliography
- References
- R13.0 Books
- R13.2 Design Considerations
- R13.3 Clock Network Design
- R13.4 Power/Ground Network Design
- Chapter 14. Fault simulation and test generation
- Bibliography
- References
- R14.0 Books
- R14.1 Fault Collapsing
- R14.2 Fault Simulation
- R14.3 Test Generation
- R14.4 Advanced Test Generation
- R14.5 Concluding Remarks
Product information
- Title: Electronic Design Automation
- Author(s):
- Release date: March 2009
- Publisher(s): Morgan Kaufmann
- ISBN: 9780080922003
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