March 2002
Intermediate to advanced
432 pages
9h
English
This section details the phases of the hardware design process for the RPX-CLLF target board. These steps are the same for the MediaEngine and the RPX-CLLF, but architectural differences between these processors warrant detailed coverage for each board.
This section details the RPX-CLLF interface hardware design. After the engineers find space in the memory map for the I/O circuit, they configure the CPU registers and test the circuit by using the helloworldbit program. The engineers then develop the RPX-CLLF liftmon_snowcon device driver, which enables the RPX-CLLF target board to monitor lifts and control snow-making ...
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