book

Event-Based Neuromorphic Systems

Name: Event-Based Neuromorphic Systems
ISBN: 9780470018491

by Shih-Chii Liu, Tobi Delbruck, Giacomo Indiveri, Adrian Whatley, Rodney Douglas

February 2015

Intermediate to advanced

440 pages

15h 37m

English

Wiley

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Coverpage
Titlepage
Copyright
Dedication
Contents
List of Contributors
Foreword
Acknowledgments
List of Abbreviations and Acronyms
1 Introduction
1.1 Origins and Historical Context1.2 Building Useful Neuromorphic SystemsReferences

Part I UNDERSTANDING NEUROMORPHIC SYSTEMS
2 Communication
2.1 Introduction2.2 Address-Event Representation2.2.1 AER Encoders2.2.2 Arbitration Mechanisms2.2.3 Encoding Mechanisms2.2.4 Multiple AER Endpoints2.2.5 Address Mapping2.2.6 Routing2.3 Considerations for AER Link Design2.3.1 Trade-off: Dynamic or Static Allocation2.3.2 Trade-off: Arbitered Access or Collisions?2.3.3 Trade-off: Queueing versus Dropping Spikes2.3.4 Predicting Throughput Requirements2.3.5 Design Trade-offs2.4 The Evolution of AER Links2.4.1 Single Sender, Single Receiver2.4.2 Multiple Senders, Multiple Receivers2.4.3 Parallel Signal Protocol2.4.4 Word-Serial Addressing2.4.5 Serial Differential Signaling2.5 DiscussionReferences
3 Silicon Retinas
3.1 Introduction3.2 Biological Retinas3.3 Silicon Retinas with Serial Analog Output3.4 Asynchronous Event-Based Pixel Output Versus Synchronous Frames3.5 AER Retinas3.5.1 Dynamic Vision Sensor3.5.2 Asynchronous Time-Based Image Sensor3.5.3 Asynchronous Parvo–Magno Retina Model3.5.4 Event-Based Intensity-Coding Imagers (Octopus and TTFS)3.5.5 Spatial Contrast and Orientation Vision Sensor (VISe)3.6 Silicon Retina Pixels3.6.1 DVS Pixel3.6.2 ATIS Pixel3.6.3 VISe Pixel3.6.4 Octopus Pixel3.7 New Specifications for Silicon Retinas3.7.1 DVS Response Uniformity3.7.2 DVS Background Activity3.7.3 DVS Dynamic Range3.7.4 DVS Latency and Jitter3.8 DiscussionReferences
4 Silicon Cochleas
4.1 Introduction4.2 Cochlea Architectures4.2.1 Cascaded 1D4.2.2 Basic 1D Silicon Cochlea4.2.3 2D Architecture4.2.4 The Resistive (Conductive) Network4.2.5 The BM Resonators4.2.6 The 2D Silicon Cochlea Model4.2.7 Adding the Active Nonlinear Behavior of the OHCs4.3 Spike-Based Cochleas4.3.1 Q-control of AEREAR2 Filters4.3.2 Applications: Spike-Based Auditory Processing4.4 Tree Diagram4.5 DiscussionReferences
5 Locomotion Motor Control
5.1 Introduction5.1.1 Determining Functional Biological Elements5.1.2 Rhythmic Motor Patterns5.2 Modeling Neural Circuits in Locomotor Control5.2.1 Describing Locomotor Behavior5.2.2 Fictive Analysis5.2.3 Connection Models5.2.4 Basic CPG Construction5.2.5 Neuromorphic Architectures5.3 Neuromorphic CPGs at Work5.3.1 A Neuroprosthesis: Control of Locomotion in Vivo5.3.2 Walking Robots5.3.3 Modeling Intersegmental Coordination5.4 DiscussionReferences
6 Learning in Neuromorphic Systems
6.1 Introduction: Synaptic Connections, Memory, and Learning6.2 Retaining Memories in Neuromorphic Hardware6.2.1 The Problem of Memory Maintenance: Intuition6.2.2 The Problem of Memory Maintenance: Quantitative Analysis6.2.3 Solving the Problem of Memory Maintenance6.3 Storing Memories in Neuromorphic Hardware6.3.1 Synaptic Models for Learning6.3.2 Implementing a Synaptic Model in Neuromorphic Hardware6.4 Toward Associative Memories in Neuromorphic Hardware6.4.1 Memory Retrieval in Attractor Neural Networks6.4.2 Issues6.5 Attractor States in a Neuromorphic Chip6.5.1 Memory Retrieval6.5.2 Learning Visual Stimuli in Real Time6.6 DiscussionReferences
Part II BUILDING NEUROMORPHIC SYSTEMS
7 Silicon Neurons
7.1 Introduction7.2 Silicon Neuron Circuit Blocks7.2.1 Conductance Dynamics7.2.2 Spike-Event Generation7.2.3 Spiking Thresholds and Refractory Periods7.2.4 Spike-Frequency Adaptation and Adaptive Thresholds7.2.5 Axons and Dendritic Trees7.2.6 Additional Useful Building Blocks7.3 Silicon Neuron Implementations7.3.1 Subthreshold Biophysically Realistic Models7.3.2 Compact I&F Circuits for Event-Based Systems7.3.3 Generalized I&F Neuron Circuits7.3.4 Above Threshold, Accelerated-Time, and Switched-Capacitor Designs7.4 DiscussionReferences
8 Silicon Synapses
8.1 Introduction8.2 Silicon Synapse Implementations8.2.1 Non Conductance-Based Circuits8.2.2 Conductance-Based Circuits8.2.3 NMDA Synapse8.3 Dynamic Plastic Synapses8.3.1 Short-Term Plasticity8.3.2 Long-Term Plasticity8.4 DiscussionReferences
9 Silicon Cochlea Building Blocks
9.1 Introduction9.2 Voltage-Domain Second-Order Filter9.2.1 Transconductance Amplifier9.2.2 Second-Order Low-Pass Filter9.2.3 Stability of the Filter9.2.4 Stabilised Second-Order Low-Pass Filter9.2.5 Differentiation9.3 Current-Domain Second-Order Filter9.3.1 The Translinear Loop9.3.2 Second-Order Tau Cell Log-Domain Filter9.4 Exponential Bias Generation9.5 The Inner Hair Cell Model9.6 DiscussionReferences
10 Programmable and Configurable Analog Neuromorphic ICs
10.1 Introduction10.2 Floating-Gate Circuit Basics10.3 Floating-Gate Circuits Enabling Capacitive Circuits10.4 Modifying Floating-Gate Charge10.4.1 Electron Tunneling10.4.2 pFET Hot-Electron Injection10.5 Accurate Programming of Programmable Analog Devices10.6 Scaling of Programmable Analog Approaches10.7 Low-Power Analog Signal Processing10.8 Low-Power Comparisons to Digital Approaches: Analog Computing in Memory10.9 Analog Programming at Digital Complexity: Large-Scale Field Programmable Analog Arrays10.10 Applications of Complex Analog Signal Processing10.10.1 Analog Transform Imagers10.10.2 Adaptive Filters and Classifiers10.11 DiscussionReferences
11 Bias Generator Circuits
11.1 Introduction11.2 Bias Generator Circuits11.2.1 Bootstrapped Current Mirror Master Bias Current Reference11.2.2 Master Bias Power Supply Rejection Ratio (PSRR)11.2.3 Stability of the Master Bias11.2.4 Master Bias Startup and Power Control11.2.5 Current Splitters: Obtaining a Digitally Controlled Fraction of the Master Current11.2.6 Achieving Fine Monotonic Resolution of Bias Currents11.2.7 Using Coarse–Fine Range Selection11.2.8 Shifted-Source Biasing for Small Currents11.2.9 Buffering and Bypass Decoupling of Individual Biases11.2.10 A General Purpose Bias Buffer Circuit11.2.11 Protecting Bias Splitter Currents from Parasitic Photocurrents11.3 Overall Bias Generator Architecture Including External Controller11.4 Typical Characteristics11.5 Design Kits11.6 DiscussionReferences
12 On-Chip AER Communication Circuits
12.1 Introduction12.1.1 Communication Cycle12.1.2 Speedup in Communication12.2 AER Transmitter Blocks12.2.1 AER Circuits within a Pixel12.2.2 Arbiter12.2.3 Other AER Blocks12.2.4 Combined Operation12.3 AER Receiver Blocks12.3.1 Chip-Level Handshaking Block12.3.2 Decoder12.3.3 Handshaking Circuits in Receiver Pixel12.3.4 Pulse Extender Circuits12.3.5 Receiver Array Peripheral Handshaking Circuits12.4 DiscussionReferences
13 Hardware Infrastructure
13.1 Introduction13.1.1 Monitoring AER Events13.1.2 Sequencing AER Events13.1.3 Mapping AER Events13.2 Hardware Infrastructure Boards for Small Systems13.2.1 Silicon Cortex13.2.2 Centralized Communication13.2.3 Composable Architecture Solution13.2.4 Daisy-Chain Architecture13.2.5 Interfacing Boards using Serial AER13.2.6 Reconfigurable Mesh-Grid Architecture13.3 Medium-Scale Multichip Systems13.3.1 Octopus Retina + IFAT13.3.2 Multichip Orientation System13.3.3 CAVIAR13.4 FPGAs13.5 DiscussionReferences
14 Software Infrastructure
14.1 Introduction14.1.1 Importance of Cross-Community Commonality14.2 Chip and System Description Software14.2.1 Extensible Markup Language14.2.2 NeuroML14.3 Configuration Software14.4 Address Event Stream Handling Software14.4.1 Field-Programmable Gate Arrays14.4.2 Structure of AE Stream Handling Software14.4.3 Bandwidth and Latency14.4.4 Optimization14.4.5 Application Programming Interface14.4.6 Network Transport of AE Streams14.5 Mapping Software14.6 Software Examples14.6.1 ChipDatabase – A System for Tuning Neuromorphic aVLSI Chips14.6.2 Spike Toolbox14.6.3 jAER14.6.4 Python and PyNN14.7 DiscussionReferences
15 Algorithmic Processing of Event Streams
15.1 Introduction15.2 Requirements for Software Infrastructure15.2.1 Processing Latency15.3 Embedded Implementations15.4 Examples of Algorithms15.4.1 Noise Reduction Filters15.4.2 Time-Stamp Maps and Subsampling by Bit-Shifting Addresses15.4.3 Event Labelers as Low-Level Feature Detectors15.4.4 Visual Trackers15.4.5 Event-Based Audio Processing15.5 DiscussionReferences
16 Towards Large-Scale Neuromorphic Systems
16.1 Introduction16.2 Large-Scale System Examples16.2.1 Spiking Neural Network Architecture16.2.2 Hierarchical AER16.2.3 Neurogrid16.2.4 High Input Count Analog Neural Network System16.3 DiscussionReferences
17 The Brain as Potential Technology
17.1 Introduction17.2 The Nature of Neuronal Computation: Principles of Brain Technology17.3 Approaches to Understanding Brains17.4 Some Principles of Brain Construction and Function17.5 An Example Model of Neural Circuit Processing17.6 Toward Neuromorphic CognitionReferences
Index

Content preview from Event-Based Neuromorphic Systems

Index

action potential, 162, 164

adaptive exponential I&F neuron, 174, 342

Address Event Representation, see AER address translation, 306

AER, 12

0.02, 28–29

2D winner-take-all, 338

4-phase handshaking, 298

active pullup, 301

address space, 32, 306, 327

arbiter, 290

arbiter interface block, 290, 295

bandwidth, 20, 334, 352

burst-mode, 16, 33

connector standard, 29–32

convolution chip, 336

daisy-chain, 324

decoder, 12, 299

encoder, 12, 13, 17, 297

fair arbiter, 293

frame conversion, 311, 312, 319, 320

greedy arbiter, 293

infrastructure, Unix pipe analogy, 318

merge circuit, 324

pre-decoder, 300

protocol, 316, 317

receiver, 306

receiver pixel, 300

sender, 306

serial (SAER), 34, 324–329

silicon retina, 40

sniffer, 310

split circuit, 324

wired OR, 302

wired OR pullup, 290

word-serial, 32–33

word-serial protocol, 332

AER channel

arbitration, 23, 26, 27

capacity, 20–27, 335

collision probability, 23, 24, 26, 27

collisions, 23, 24, 26, 27

contention, 23, 27

dispersion, 20, 21, 23, 24, 26, 27

integrity, 20, 21

jitter, 354

latency, 20, 21, 24–27

load, 20, 23–25, 27

queuing, 23, 24

throughput, 20, 22, 25–27

timing error, 24, 25, 27

waiting time, 24

AEREAR, see silicon cochlea

AEX, 324–325, 326, 341

ALAVLSI, 350, 358

algorithmic event processing, 365–379

algorithmic mapping, 315

ALOHA, 27

amacrine cell, 47

amplifier, 239

analog signal processing, 249, 253

API, 355, 356, 360, 362

Application Programming Interface, see API APS, 51, 64

arbitration, 13, 21

greedy tree, 15

multidimensional, ...

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Event-Based Neuromorphic Systems

by Shih-Chii Liu, Tobi Delbruck, Giacomo Indiveri, Adrian Whatley, Rodney Douglas

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