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Field-Programmable Gate Arrays: Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems by Richard C. Dorf, John V. Oldfield

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4.4   DESIGN PROCESS FLOW: THE APPLICATION-SPECIFIC INTEGRATED CIRCUIT ROUTE

There are many sources of ASIC design process flows. VLSI design methodologies [Mead80], [Weste93] and ASIC manufacturers [Naish88] are good sources. The former place greater emphasis on layout issues, such as wiring management, to achieve optimal physical designs, while the latter largely rely on structural design to manage the whole process flow. A generic model for ASIC process flow is shown in Figure 4–8. Both the Gajski-Kuhn and more traditional forms are shown. This indicates the refinement of a specification to a structural design before entering design validation and physical design processes. In reality the behavioral and structural descriptions are built by stepwise refinement of the design. A typical ASIC design process flow, represented by paths in the Gajski-Kuhn diagram, shows the three design descriptions being built and the grain of the design unit decreasing. Thus a starting behavioral specification posits a structural design. This could be a composition of interconnected function units. This, in turn, could be stepwise refined by expanding to a structural design of simple elements, a gate-level netlist, or synthesizing a two-level logic block.

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Figure 4–8. ASIC design process flow.

To illustrate the flow let us return to the display driver example. In fact, the 7-segment display driver ...

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