book

FPGA Programming for Beginners

Name: FPGA Programming for Beginners
Author: Frank Bruno
ISBN: 9781789805413

by Frank Bruno

March 2021

Beginner

368 pages

6h 54m

English

Packt Publishing

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FPGA Programming for Beginners
ContributorsAbout the authorAbout the reviewer
Preface
Who this book is forWhat this book coversTo get the most out of this bookDownload the example code filesDownload the color imagesConventions usedGet in touchReviews
Section 1: Introduction to FPGAs and Xilinx Architectures
Chapter 1: Introduction to FPGA Architectures and Xilinx Vivado
Technical requirementsHardwareSoftwareWhat is an ASIC?Why an ASIC or FPGA?How does a company create a programmable device using an ASIC process?Fundamental logic gatesAssign statementCommentsif statementLogical NOT (!)Logical AND (&&), bitwise AND (&)Logical OR (||), bitwise OR (|)XOR (^)More complex operationsIntroducing FPGAsExploring the Xilinx Artix-7 and 7 series devicesCombinational logic blocksStorageClockingI/OsDSP48E1ASMBL architectureIntroduction to the Vivado toolset and evaluation boardsEvaluation boardsNexys A7 100T (or 50T)Basys 3Introducing VivadoVivado installationDirectory structureRunning the exampleLoading the designRunning a simulationImplementationProgram the boardSummaryQuestionsChallenge Further reading
Section 2: Introduction to Verilog RTL Design, Simulation, and Implementation
Chapter 2: Combinational Logic
Technical requirementsCreating SystemVerilog modulesHow to create reusable code – parametersIntroducing data typesIntroducing built-in data typesCreating arraysQuerying arraysAssigning to arraysHandling multiple-driven netsHandling signed and unsigned numbersAdding bits to a signal by concatenatingCasting signed and unsigned numbersCreating user-defined typesAccessing signals using values with enumerated typesPackaging up code using functionsCreating combinational logicHandling assignment operatorsIncrementing signalsMaking decisions – if-then-elseIntroducing the case statement Using the conditional operator to select dataUsing custom data typesCreating structuresCreating unionsProject 1 – creating combinational logicTestbenchSimulating using targeted testingSimulating using randomized testingSimulating using constrained randomizationImplementing a leading-one detector using the case statementControlling implementation using generateDesigning a reusable leading-one detector using a for loopSetting SELECTOR = DOWN_FORSetting SELECTOR = UP_FORCounting the number of onesImplementing an adder/subtractorAddSubtractorMultiplierBringing it all togetherAdding a latchSummaryQuestionsChallengeFurther reading
Chapter 3: Counting Button Presses
Technical requirementsWhat is a sequential element?Clocking your designLooking at a basic registerCreating a flip flopWhen to use always @() for FF generationUsing non-blocking assignmentsRegisters in the Artix 7How to hold onto state using clock enablesResetting the FFProject 2 – Counting button pressesIntroducing the seven-segment displayDetecting button pressesAnalyzing timingLooking at asynchronous issuesUsing the asynchronous signal directlyThe problem with push buttonsDesigning a safe implementationSwitching to decimal representationIntroducing the ILAWhat about simulation?Deep dive on synchronizationWhy use multiple clocks?Two-stage synchronizerSynchronizing control signalsPassing dataSummaryQuestionsChallengeFurther reading
Chapter 4: Let's Build a Calculator
Technical requirementsImplementing our first state machineWriting a purely sequential state machineSplitting combination and sequential logic in a state machineDesigning a calculator interfaceDesigning a Moore state machineImplementing a Mealy state machinePractical state machine designProject 3 – Building a simple calculatorPackaging for reuseCoding the top levelChanging frequencies by using a PLL or MMCMInvestigating the dividerBuilding a non-restoring divider state machineSimulating the dividerSizing the intermediate remainderProject 4 – Keeping cars in lineDefining the state diagramDisplaying our traffic lightsPulse width modulationImplementing delays with a counterSummaryQuestionsChallengeExtra challengeFurther reading
Chapter 5: FPGA Resources and How to Use Them
Technical requirementsProject 5 – Listening and learningWhat is a PDM microphone?Simulating the microphoneIntroducing storageRAM – Inferring versus instantiating versus the IP catalogBasic RAM typesInstantiating memories using xpm_memoryUsing the IP catalog to create memoryCapturing audio dataProject 6 – Using the temperature sensorHandling the dataSmoothing out the dataDeeper dive into FIFOsConstraintsGenerating our FIFOSummaryQuestionsFurther reading
Chapter 6: Math, Parallelism, and Pipelined Design
Technical requirementsIntroduction to fixed-point numbersProject 7 – Using fixed-point arithmetic in our temperature sensorUsing fixed-point arithmetic to clean up the bring-up timeTemperature conversion using fixed-point arithmeticWhat about floating-point numbers?Floating-point addition and subtractionFloating-point multiplicationFloating-point reciprocalA more practical floating-point operation libraryA quick look at the AXI streaming interfaceProject 8 – Updating the temperature sensor project to a pipelined floating-point implementationFix to floating point conversionFloating-point math operationsFloat to fixed point conversionSimulationParallel designsML and AI and massive parallelismParallel design – a quick exampleSummaryQuestionsChallengeFurther reading

Section 3: Interfacing with External Components
Chapter 7: Introduction to AXI
Technical requirementsAXI streamingProject 9 – creating IPs for Vivado using AXI streaming interfacesSeven-segment display streaming interfaceDeveloping the ADT7420 IPUnderstanding the flt_temp coreIP integratorIP integrator debuggingAXI4 interfaces (full and AXI-Lite)Developing IPs – AXI-Lite, full, and streamingAdding an unpackaged IP to the IP integratorSummaryQuestionsFurther reading
Chapter 8: Lots of Data? MIG and DDR2
Technical requirementsProject 10 – introducing external memoryIntroduction to DDR2Generating a DDR2 controller using the Xilinx MIGSetting AXI parametersSetting memory optionsDefining the FPGA optionsModifying the design for use on the boardOther external memory typesQuad Data Rate (QDR) SRAM HyperRAMSPI RAMSummaryQuestionsChallengeFurther reading
Chapter 9: A Better Way to Display – VGA
Technical requirementsProject 11 – Introducing the VGADefining registersCoding a simple AXI Lite interfaceGenerating timing for the VGAMonitor timing generatorDisplaying textRequesting memoryTesting the VGA controllerExamining the constraintsSummaryQuestionsChallengeFurther reading
Chapter 10: Bringing It All Together
Technical requirementsInvestigating the keyboard interfaceProject 12 – keyboard handlingTesting the PS/2Project 13 – bringing it all togetherDisplaying PS/2 keycodes on the VGA screenDisplaying the temperature sensor dataAdding a custom character to the text ROMDisplaying audio dataSummaryQuestionsChallengeFurther reading
Chapter 11: Advanced Topics
Technical requirementsExploring more advanced SystemVerilog constructsInterfacing components using the interface constructUsing structuresBlock labelsLooping using for loopsLooping using do…whileExiting a loop using disableSkipping code using continueUsing constantsExploring some more advanced verification constructsIntroducing SystemVerilog queuesDisplay enhancementsA quick introduction to assertionsUsing $error or $fatal in synthesisOther gotchas and how to avoid themInferring single bit wiresBit width mismatchesUpgrading or downgrading Vivado messagesHandling timing closureHow to pipeline a designSummaryQuestionsFurther reading
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Content preview from FPGA Programming for Beginners

Chapter 2: Combinational Logic

Designs are typically composed of combinational and sequential logic. Combinational logic is made up simply of gates, as we saw in Chapter 1, Introduction to FPGA Architectures and Xilinx Vivado. Sequential logic maintains state, usually based on a clock edge, but it can be level-based as well, as we will discuss when we learn what not to do when inferring sequential logic.

In this chapter, we are going to explore writing a complete SystemVerilog module from scratch that can perform some basic real-world operations that you may use one day in your actual designs.

In this chapter, we are going to cover the following main topics:

Creating SystemVerilog modules
Introducing data types
Packaging up code using functions ...

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FPGA Programming for Beginners

by Frank Bruno

Chapter 2: Combinational Logic

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