
Performance Considerations and Modern Systems 185
TABLE 8.2: Latencies observed in an Itanium-2 based distributed
memory system with both Infiniband and Gigabit Ethernet intercon-
nection networks.
Source of latency Cycle count
L1 cache 1-2
L2 cache 5-7
L3 cache 12-21
Main memory 180-225
Gigabit Ethernet (access to remote node) approx. 45,000 (30 µs)
Infiniband (access to remote node) approx. 7,500 (5 µs)
or data layout of a complex data structure in memory to a compiler, we can
allow it to determine the ideal implementation based on its knowledge of the
target platform. On the other hand though, we lose the ability to perform
tuning when the high-level abstraction ...