Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL

9.5 STATE ASSIGNMENT

Recall that the state assigned table is constructed by assigning randomly binary numbers to the states of the FSM. The problem is that there is no priori knowledge to determine which state assignment sequence would produce a minimum circuit implementation. To illustrate the effects of state assignment, consider the state assigned table shown in Figure 9.13. An alternative state assigned table is shown in Figure 9.24, where the binary values of states S₂ and S₃ were switched. States S₂ and S₃ are assigned the binary numbers 11 and 10, respectively.

Next states Y₁ and Y₂ and output z logic expressions are derived using the Karnaugh maps shown in Figure 9.25. Using D flip-flops, the circuit implementation of the FSM is illustrated in Figure 9.26. Notice that the combinational circuit of the FSM has fewer logic gates than the implementation circuit in Figure 9.15. This example illustrates that different state assignments generate different implementation circuits with varying degrees of complexity. Although there is no simple way to guess an appropriate state assignment, a visual inspection of Karnaugh maps of an initial state assignment would give insights on how to modify the Karnaugh maps to obtain reduced implicants, which generate combinational circuits with fewer logic gates. Of course, for a larger number of states, visual inspections become impossible. As mentioned before, modern CAD tools use proprietary methods to generate optimized implementations.