Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL

9.4 FINITE-STATE MACHINE SYNTHESIS

Synthesis is the process of designing a finite-state machine from a problem statement which describes its specifications and behavior. We use the design procedures provided in Section 9.3.4, with the exception of state minimization, which is covered in detail in Section 9.8. We will implement a simple finite-state machine using Moore and Mealy models to illustrate similarities and differences between the two models. The finite-state machine is designed using D flip-flops. In Section 9.8 we describe how to use other flip-flops, such as JK and T flip-flops.

Below we work with a finite-state machine with one input, x, and one output, z. Output z is equal to 1 when the sequence 111 has been detected at the input; otherwise, output z is equal to 0. This finite-state machine is referred to as a sequence detector.

9.4.1 Moore Model Design

Recall that in the Moore model, the output of a finite-state machine depends only on the present states of the machine. Therefore, input sequence 111 would have occurred in the precedingthree clock cycles for output z to change to 1. A sample input-output time sequence is illustrated inFigure 9.10. Notice that output z changes to 1 only if input x was equal to 1 during the preceding three clock cycles. As long as input x is equal to 0, there is no change in the state memory of output z of the FSM. Therefore, we select state S₀ as a starting state, where input x is equal to 0 and output z is equal to 0. If input x remains ...